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Single Logic Cell Test Latch for AC Testing of Embedded Arrays

IP.com Disclosure Number: IPCOM000061482D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Torku, KE: AUTHOR [+2]

Abstract

High performance embedded arrays require accurately measured AC timings during test. Read Access Time measurements, in particular, are unduly influenced by receiver and driver delays which are added to the performance of the RAM (random-access memory). By use of the test latch described in this article, access times may be determined without these complications, thereby greatly increasing the accuracy of measurement. Referring to Fig. 1, a test latch TL is used between the array AR and the driver DR, to latch the output data before going to the driver. An array data output signal DO can be used to set the latch, and an external test clock signal TC can be used to prevent the latch from changing. If the array data output signal occurs before the specified clock reset signal, then the access time is acceptable.

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Single Logic Cell Test Latch for AC Testing of Embedded Arrays

High performance embedded arrays require accurately measured AC timings during test. Read Access Time measurements, in particular, are unduly influenced by receiver and driver delays which are added to the performance of the RAM (random-access memory). By use of the test latch described in this article, access times may be determined without these complications, thereby greatly increasing the accuracy of measurement. Referring to Fig. 1, a test latch TL is used between the array AR and the driver DR, to latch the output data before going to the driver. An array data output signal DO can be used to set the latch, and an external test clock signal TC can be used to prevent the latch from changing. If the array data output signal occurs before the specified clock reset signal, then the access time is acceptable. If it occurs following the clock TC signal, the test data output at the driver output will be the opposite of the expected state, and the chip would be rejected. The T1 and T0 signals of Fig. 1 are complements of each other, being used to multiplex between system and test modes of operation. In normal system operation, the test latch is inhibited and the off-chip driver in series with the latch is multiplexed with the system logic circuitry (AI3 of Fig. 1.). A large number of data outputs are required in an embedded array and the test latch implementation can become critical with respect to chip...