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Address Translation for Memory Unit With Non-Uniform Array Card Sizes

IP.com Disclosure Number: IPCOM000061500D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Barbash, WA: AUTHOR

Abstract

A fast translation mechanism converts the absolute addresses provided to a memory unit to corresponding physical addresses useable by the memory unit, which is comprised of cards of non-uniform size. Non- identical groups of cards provide the bit width dimension to the memory unit, with one card from each group accessed at the same time from the same absolute address. The total addressable size of each group is the same. In a memory unit, where the data spans multiple cards and groups, the address for an access results in the selection of one card within each group, as well as the correct memory location within each card.

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Address Translation for Memory Unit With Non-Uniform Array Card Sizes

A fast translation mechanism converts the absolute addresses provided to a memory unit to corresponding physical addresses useable by the memory unit, which is comprised of cards of non-uniform size. Non- identical groups of cards provide the bit width dimension to the memory unit, with one card from each group accessed at the same time from the same absolute address. The total addressable size of each group is the same. In a memory unit, where the data spans multiple cards and groups, the address for an access results in the selection of one card within each group, as well as the correct memory location within each card. For a conventionally organized memory, with equal binary increment sized cards, the corresponding cards in the different groups are selected by the high-order address bits, and the low-order address bits select the location within the card. For cards of non-uniform size, the address bits for card and array data selection are first converted to the physical address by the fast translation mechanism incorporated within the array cards in the memory unit. The table shows the required translation from absolute to physical address for one group of four cards. The cards range in size from 1 to N times a basic binary size (N=4 for illustration). Since N is any integer, the array card size need not be a binary increment of the basic binary size. Two implementations of the address tran...