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Browse Prior Art Database

Command Response Bus System With Inherent Fault-Isolation Features

IP.com Disclosure Number: IPCOM000061504D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Balliet, L: AUTHOR [+3]

Abstract

This article describes a system arrangement which provides topology and logic for isolating faulty components while retaining features of a multi-point command/response distribution and control structure. The low cost and programmability of microprocessor-based hardware has made multi-unit federated systems feasible and attractive. Such systems, for example, will be used extensively in high volume production automobiles to interconnect units for engine control, body control, display, temperature, entertainment and other functions. In such applications serviceability and availability are very important and it is consequently desirable to detect and isolate electronic component faults quickly while maintaining a functioning system.

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Command Response Bus System With Inherent Fault-Isolation Features

This article describes a system arrangement which provides topology and logic for isolating faulty components while retaining features of a multi-point command/response distribution and control structure. The low cost and programmability of microprocessor-based hardware has made multi-unit federated systems feasible and attractive. Such systems, for example, will be used extensively in high volume production automobiles to interconnect units for engine control, body control, display, temperature, entertainment and other functions. In such applications serviceability and availability are very important and it is consequently desirable to detect and isolate electronic component faults quickly while maintaining a functioning system. Multi-point/command response serial bus architecture is commonly implemented by microprocessor chips commercially available today. A typical system, as illustrated in Fig. 1, will have a serial bus interconnected via drivers (transmitters) and receivers connected to a common wire or wire pair. Bus protocol is determined by integrated circuit UARTs, (universal asynchronous receiver-transmitter) or microcomputers that have a built-in UART function. The system has advantages in that data, available to all terminals directly from the common bus units (terminals), can be added or removed without altering bus network structure; standard protocol and low cost commercially-available microcomputer and UART components can be used. However, this system interconnection can have certain failures on the bus interrupt communication and prevent automated fault isolation and fault circumvention. For example, a driver can be stuck transmitting or a short can be caused by driver, receiver or connector components. Isolation of such failures is very difficult. An identical redundant bus would permit continued communication but would not ease fault isolation. The system arrangement herein solves the problem of fault isolation and circumvention while remaining compatible with the low cost command/ response microprocessor hardware. Fig. 2 shows the present system in simplified form. The system hereafter called serial fault isolation bus contains microprocessor and micro-computer units as in Fig. 1, but instead of being coupled directly to a common multi-point bus, each microprocessor-based unit interfaces through a logic switch (LS) which in turn operates through two loops A and B, respectively. Each unit also has two receivers 4 and 5 and two drivers 6 and 7. The LS 1 determines the data path flow on the bus (or buses). With command/response bus architecture, one of the units serves as a bus controller initiating all data transmissions. Other units (referred to here as slave units) are free to transmit only after receiving a request or "offer" by the bus controller. For the serial fault isolation bus, normal communication (with no faults) will be through bus A w...