Browse Prior Art Database

Low Power CMOS General-Purpose Interface Receiver With a Clocked-Gate Option

IP.com Disclosure Number: IPCOM000061513D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Kim, IW: AUTHOR

Abstract

This article describes a CMOS general-purpose interface (GPI) receiver designed to reduce power requirements, and features a clocked gate output option which may be used as a control feature for other GPI receivers. Previous GPI receiver circuits consumed substantial amounts of power because the input drive transistor was always turned on to meet the initial load current requirements presented by the output load when gated. The circuit shown in Fig. 1 was designed so that the initial high load (output) current demands are met by driver T1 after which time the load current demands are substantially reduced and are transferred to driver T9 which is designed to supply much smaller current loads. T1 is turned off post drive to conserve power.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Low Power CMOS General-Purpose Interface Receiver With a Clocked-Gate Option

This article describes a CMOS general-purpose interface (GPI) receiver designed to reduce power requirements, and features a clocked gate output option which may be used as a control feature for other GPI receivers. Previous GPI receiver circuits consumed substantial amounts of power because the input drive transistor was always turned on to meet the initial load current requirements presented by the output load when gated. The circuit shown in Fig. 1 was designed so that the initial high load (output) current demands are met by driver T1 after which time the load current demands are substantially reduced and are transferred to driver T9 which is designed to supply much smaller current loads. T1 is turned off post drive to conserve power. This circuit allows a 10:1 power reduction through the use of p-channel drivers in parallel (T1 and T9). The circuit feedback control mechanism is implemented through a series of inverters made up of pairs of p-channel and n-channel devices, i.e., T2 and T5, T3 and T6 and T4 and T7, respectively. When node A is positive, node B is negative, node C is positive and node D is negative. Node B controls the alternate driver T9 and node C controls the initial driver T1. Node C is also used to drive output node D and an optional clocked-gate output. Referring to the timing diagram in Fig. 2, when Input-not is high, T8 is on, nodes A and C are at ground and nodes B and D are high. Node B holds off T9 and drives node C. Node C holds T1 on, drives the output node D and the optional clocked-gate outputs. When Input-not falls, T8 is turned off, nodes A and C rise and nodes B and D fall. Node B turns T9 on, and node C turns T1 off, transferring the output load to T9 which accounts for the circuit's power conservation attributes. Fig. 3 shows the GPI circuit used as a Chip Select (CS) receiver utilizing the clocked-gate output...