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Concurrent Analog-To-Digital and Digital-To-Analog Converter Using Serial Approximation Register

IP.com Disclosure Number: IPCOM000061514D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Zalph, W: AUTHOR

Abstract

A technique is described whereby serial approximation register (SAR) - analog-to-digital (A/D) technology is used to incorporate concurrent digital-to-analog (D/A) and analog-to-digital conversion into one integrated circuit with less than a ten percent increase in circuits beyond an SAR A/D converter. A conventional SAR A/D conversion circuit is shown in Fig. 1. At the start of conversion, SAR 10 is cleared and the D/A 11 converts the output 12, on the digital bus 17, to analog form 20 to be compared to the analog input signal voltage 13. When the D/A output equals the analog input, comparator 14 switches, signalling that the digital output 12 of the SAR is correct. The SAR sequencing is then disabled and the output latch 15 acquires and holds the correct output data. SAR 10 output is then tri-stated.

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Concurrent Analog-To-Digital and Digital-To-Analog Converter Using Serial Approximation Register

A technique is described whereby serial approximation register (SAR) - analog- to-digital (A/D) technology is used to incorporate concurrent digital-to-analog (D/A) and analog-to-digital conversion into one integrated circuit with less than a ten percent increase in circuits beyond an SAR A/D converter. A conventional SAR A/D conversion circuit is shown in Fig. 1. At the start of conversion, SAR 10 is cleared and the D/A 11 converts the output 12, on the digital bus 17, to analog form 20 to be compared to the analog input signal voltage 13. When the D/A output equals the analog input, comparator 14 switches, signalling that the digital output 12 of the SAR is correct. The SAR sequencing is then disabled and the output latch 15 acquires and holds the correct output data. SAR 10 output is then tri-stated. The cycle repeats with a begin convert signal 16 which clears SAR 10 and re-enables sequencing on digital bus 17. The concurrent A/D - D/A converter, as shown in Fig. 2, has the identical circuit for A/D conversion of Fig. 1, but with the addition of D/A conversion capabilities. For D/A operation, SAR 10 remains tri-stated off since no begin A/D convert signal occurs. The A/D output latch 15 holds the correct A/D output data from its previous conversion. The convert select switch 18 is set to select D/A conversion which allows input data latch 19 to write onto the digi...