Browse Prior Art Database

Simulated Stress Tester Assembly

IP.com Disclosure Number: IPCOM000061516D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Carden, TF: AUTHOR [+2]

Abstract

This test assembly simulates the module environment of a thermally enhanced integrated circuit (IC) chip which is surface mounted to a chip carrier by controlled collapse chip connections (C4). It provides for the measurement of forces and stresses which would be experienced by the chip and hence its C4 connections in its prototype module environment. In the assembly 10, the module environment is simulated by the pinned ceramic substrate S, module cover C and a known quantity of thermal grease (not shown) which is placed in the space under the cover C. A sample chip (not shown) is located in the environment and is mounted to a stainless steel plate P. Alternatively, the plate P itself may be used to simulate the chip.

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Simulated Stress Tester Assembly

This test assembly simulates the module environment of a thermally enhanced integrated circuit (IC) chip which is surface mounted to a chip carrier by controlled collapse chip connections (C4). It provides for the measurement of forces and stresses which would be experienced by the chip and hence its C4 connections in its prototype module environment. In the assembly 10, the module environment is simulated by the pinned ceramic substrate S, module cover C and a known quantity of thermal grease (not shown) which is placed in the space under the cover C. A sample chip (not shown) is located in the environment and is mounted to a stainless steel plate P. Alternatively, the plate P itself may be used to simulate the chip. A cutout 1 is formed in substrate S at the substrate's chip-mounting site and houses a commercially available miniature transducer,
i.e., load cell 2, with the actuator or button 3 of cell 2 being bonded to the plate P. A stainless steel backing plate 4 is bonded to the bottom of cell 2 and the rim 5 of plate 4 surrounds cutout 1 and is bonded to the bottom surface of substrate S. A room temperature vulcanizer (RTV) seal is used between the body of cell 2 and walls of the cutout 1 to minimize stresses due to thermal mismatch. The height h is judiciously selected to correspond to the spacing encountered between the substrate carrier and the chip bonded thereto by the C4 connections in the module prototype. As a result...