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R-2R Multiplexing Digital-To-Analog Converter

IP.com Disclosure Number: IPCOM000061518D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Haas, WE: AUTHOR

Abstract

The R-2R digital-to-analog converter (DAC) uses multiplexing to connect the ladder output for each bit to all of the current sinks in sequence. A conventional R-2R DAC consists of an R-2R resistor ladder with a node for each input bit, a bit switch for each node and a current sink for each bit switch, as shown in Fig. 1. In such DACs, the DAC analog output does not always monotonically increase or decrease with corresponding increases or decreases in changes in the input bit values because of unequal current flow in the different current sinks connected to each bit. In the present design, a multiplexer driver switches each of the bits to each of the different current sinks in sequence so that the DAC analog output is an average current value. The operation of the DAC of the present design is explained by reference to Fig. 2.

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R-2R Multiplexing Digital-To-Analog Converter

The R-2R digital-to-analog converter (DAC) uses multiplexing to connect the ladder output for each bit to all of the current sinks in sequence. A conventional R-2R DAC consists of an R-2R resistor ladder with a node for each input bit, a bit switch for each node and a current sink for each bit switch, as shown in Fig. 1. In such DACs, the DAC analog output does not always monotonically increase or decrease with corresponding increases or decreases in changes in the input bit values because of unequal current flow in the different current sinks connected to each bit. In the present design, a multiplexer driver switches each of the bits to each of the different current sinks in sequence so that the DAC analog output is an average current value. The operation of the DAC of the present design is explained by reference to Fig. 2. The DAC current value is determined by the bit switches SB1 through SBn . During the first clock period, each of the current multiplexer switches SMn-m through SMm will connect its associated bit switch to a different current sink, ISn-m through ISn . It should be noted, as shown in Fig. 2, that not all R-2R nodes need be included in the multiplexer; only the m- most significant bits are required, m being a function of component tolerances. During the next clock period each bit switch will be connected to the next current sink in the group SMn-m through SMm . This multiplexing action will continue...