Browse Prior Art Database

Multiprocessor Synchronization for Automatic Inspection

IP.com Disclosure Number: IPCOM000061522D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Pfeffer, E: AUTHOR [+3]

Abstract

For quality and functionality, products have to be inspected at different stages during their manufacture to ensure that they are defect- free and that their dimensions are correct. Defects in patterns, such as are used in circuit boards or photolithographic masks, are detected by comparison with desired patterns or design data. The proposed multiprocessor architecture assumes that the image to be inspected is digitally stored in several image stores. According to the resolution of the image sensor (TV camera), these image stores are two-dimensional comprising 512 x 512 pels (picture elements) with 8-bit grey value representation for each pel. This image information must be compared within the shortest possible time with a desired pattern which, as a rule, is defined in the form of design data.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Multiprocessor Synchronization for Automatic Inspection

For quality and functionality, products have to be inspected at different stages during their manufacture to ensure that they are defect- free and that their dimensions are correct. Defects in patterns, such as are used in circuit boards or photolithographic masks, are detected by comparison with desired patterns or design data. The proposed multiprocessor architecture assumes that the image to be inspected is digitally stored in several image stores. According to the resolution of the image sensor (TV camera), these image stores are two- dimensional comprising 512 x 512 pels (picture elements) with 8-bit grey value representation for each pel. This image information must be compared within the shortest possible time with a desired pattern which, as a rule, is defined in the form of design data. The actual and desired patterns are compared by means of known algorithms such that the edge curve of the actual pattern is inspected for straightness, marking all pels positioned in the edge profile area of a black-white transition. For that purpose, each pel is associated with a grey value by setting the least significant bit (LSB) to "1" after the pel has been processed. For the inspection steps, for example, that are directed at detecting isolated defects, mark bits are used to distinguish between pattern contours complying with the design data and isolated defects. Generally, only one microprocessor is capable of accessing the image data. For that purpose, the image to be inspected is stored in several image stores. The number of image stores may be chosen at random, increasing the processing speed linearly to the number of image stores employed. Fig. 1 is a block diagram of the processor architecture with eight image stores IM1 to IM8. At the start of inspection, all image stores are loaded in parallel with the same image data, setting their mark bit to "0". A supervisor processor (SUPERVISOR PROC), storing the design data of the entire pattern, loads the edge coordinates of the polygon to be inspected (Fig. 2) into microprocessors PROC1 to PROC8. PROC1 thus receives the coordinates for vector 1, PROC2 the coordinates for vector 2, etc. After a vector has been inspected, PROC1 to PROC8 transmit defective coordinates, if any, to SUPERVISOR PROC which, in turn, distributes further vector coordinates to processors PROC1 to PROC8 until all polygons of the pattern have been inspected. During inspection, all processed pels are marked in the image stores, the corresponding areas being hatched in Fig. 2 and may be arbitrarily positioned within the image store. For each image store, only 1/8th of the polygons are inspected, thus increasing the processin...