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Loading Test Patterns Into Complex Semiconductor Chips Using Isolated Outboard Level Sensitive Scan Design Chains

IP.com Disclosure Number: IPCOM000061529D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Guhman, GF: AUTHOR

Abstract

This article describes a technique which will minimize the number of semiconductor chip I/O pads required to load level sensitive scan design (LSSD) test patterns into complex static logic designs for test purpose stimulation. Normally, a semiconductor chip may have hundreds of peripheral I/O pads, most or all of which are conventionally used by a tester as probe points in a LSSD test procedure. By designing a chip with an additional LSSD shift register in and around the pad area, a chip can be operated in test mode utilizing the shift register content instead of tester probe inputs to provide the test patterns to the chip pads needed to operate or diagnose chip problems.

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Loading Test Patterns Into Complex Semiconductor Chips Using Isolated Outboard Level Sensitive Scan Design Chains

This article describes a technique which will minimize the number of semiconductor chip I/O pads required to load level sensitive scan design (LSSD) test patterns into complex static logic designs for test purpose stimulation. Normally, a semiconductor chip may have hundreds of peripheral I/O pads, most or all of which are conventionally used by a tester as probe points in a LSSD test procedure. By designing a chip with an additional LSSD shift register in and around the pad area, a chip can be operated in test mode utilizing the shift register content instead of tester probe inputs to provide the test patterns to the chip pads needed to operate or diagnose chip problems. As shown in the figure, a test pattern is loaded into the shift register 10 through an input pad 11 and advanced through the shift register by clock pulses (not shown) until the data is latched adjacent to the chip pads 12 to be stimulated. By means of a control pulse on gate 13, the contents of the shift register 10 are gated broadside to only those pads that require stimulation. The chip clock is then cycled to sample the data at the chip pads 12 before the shift register isolation is restored by opening gate 13. This cycle is repeated (i.e., load data into the shift register, shift, and gate to pad) until the desired test pattern results in the internal logic being tested. The res...