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Reflective Random-Access Memory

IP.com Disclosure Number: IPCOM000061531D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Quinn, TP: AUTHOR [+2]

Abstract

The RRAM (reflective random-access memory) is a multi-ported memory that may be read or written to concurrently by all the processors connected to it. The RRAM consists of a plurality of random-access memories (RAMs) arranged in plains with each RAM or plain tied to a different processor via standard address, data, and control logic lines so that the state of one memory cell in a given plain is reflected to all the cells in the corresponding position in all the other plains. The reflective action between plains of the RRAM is performed through the parallel voltage-controlled gate structure shown in Fig. 2. The voltage controlling the gate of Q1 (Fig. 1) is instantaneously applied to the gate of Q1', Q1'', Q1'''. This identical effect controls all the Q2 FETs.

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Reflective Random-Access Memory

The RRAM (reflective random-access memory) is a multi-ported memory that may be read or written to concurrently by all the processors connected to it. The RRAM consists of a plurality of random-access memories (RAMs) arranged in plains with each RAM or plain tied to a different processor via standard address, data, and control logic lines so that the state of one memory cell in a given plain is reflected to all the cells in the corresponding position in all the other plains. The reflective action between plains of the RRAM is performed through the parallel voltage-controlled gate structure shown in Fig. 2. The voltage controlling the gate of Q1 (Fig. 1) is instantaneously applied to the gate of Q1', Q1'', Q1'''. This identical effect controls all the Q2 FETs. This structure causes any state transition of a cell on a plain to happen simultaneously to the corresponding cells on all other plains. Contention between processors arises when two or more processors tied to the RRAM bank try to access the same exact RRAM address. Simultaneous use occurs: 1. when two or more processors read the same RRAM address [READ/READ], 2. when one or more processors are reading while one processor is writing to a RRAM address [READ/WRITE], and 3. when two or more processors are writing to the same RRAM address [WRITE/WRITE]. There is no contention problem with the READ/READ condition. All the processors have the ability to read any RRAM address at the...