Browse Prior Art Database

Off-Chip Power Supply Decoupling Via N-Well

IP.com Disclosure Number: IPCOM000061538D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Penoyer, RF: AUTHOR

Abstract

This article describes a technique for utilizing the complementary metal oxide silicon (CMOS) technology n-wells to supply the high on- chip currents of short duration (WI's) from a low impedance on-chip source. The inherently large capacitance between n-well and substrate provides a ready-made on-chip charge source which may be used to sink high current spikes of short duration which appear on a chip power supply (VH) bus. Fig. 1 shows an n-well structure 10 needed in the CMOS n-well technology for p-channel devices 11. The n-well bias (VNW) of approximately + 6 volts and substrate bias (VSUB) of approximately - 1 volt are needed to prevent forward biasing of the p-channel junction of device 11, resulting in latch-up with a supply voltage (VH) of approximately + 5 volts.

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Off-Chip Power Supply Decoupling Via N-Well

This article describes a technique for utilizing the complementary metal oxide silicon (CMOS) technology n-wells to supply the high on- chip currents of short duration (WI's) from a low impedance on-chip source. The inherently large capacitance between n-well and substrate provides a ready-made on-chip charge source which may be used to sink high current spikes of short duration which appear on a chip power supply (VH) bus. Fig. 1 shows an n-well structure 10 needed in the CMOS n-well technology for p-channel devices 11. The n-well bias (VNW) of approximately + 6 volts and substrate bias (VSUB) of approximately - 1 volt are needed to prevent forward biasing of the p-channel junction of device 11, resulting in latch-up with a supply voltage (VH) of approximately + 5 volts. Note that in CMOS n-well technology the n- channel device 12 does not have a well structure. Fig. 2 shows an n-well bus (VNW) 15 which couples all on-chip n-wells together into a capacitor bank, i.e., Cnw1, Cnw2, Cnw3....CnwN and through n-channel device T1 to the VH bus. The VH bus has an impedance (ZVHB) made up of resistance, capacitance and inductance across which current drawn to satisfy on-chip current spikes causes VH to drop to VNW minus a threshold (VT). When the VH bus potential drops a threshold (VT) below the n-well bus bias potential (VNW), T1 turns on, connecting all n-wells as one charge source to the VH bus to meet the WI requirements....