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Scan String FLUSH Test for Product Performance

IP.com Disclosure Number: IPCOM000061545D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Gargiulo, NT: AUTHOR

Abstract

This article describes a technique for using shift register latch (SRL) strings in a logic chip design where level sensitive scan design (LSSD) ground rules are used to measure process-induced AC chip performance variations, to correlate measured results with precalculated delay data to predict chip functional performance and to use that correlation as the basis for a performance measurement test. Performance of a logic chip is limited by delays associated with the worst-case critical path which is defined as the longest functional path through a chip. By correlating the measured stage delays in a sample string of circuits on a chip with precalculated delay data, expected performance of a product chip can be established.

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Scan String FLUSH Test for Product Performance

This article describes a technique for using shift register latch (SRL) strings in a logic chip design where level sensitive scan design (LSSD) ground rules are used to measure process-induced AC chip performance variations, to correlate measured results with precalculated delay data to predict chip functional performance and to use that correlation as the basis for a performance measurement test. Performance of a logic chip is limited by delays associated with the worst-case critical path which is defined as the longest functional path through a chip. By correlating the measured stage delays in a sample string of circuits on a chip with precalculated delay data, expected performance of a product chip can be established. The LSSD design ground rules allow inaccessible latches embedded in a logic chip design to be chained together to form a shift register format for test purposes. By using a technique known as "scan string flush", a series of shift register logic elements are chained together to form a long delay line which is used to accurately time data flushed through the string. The delay information obtained is used as the basis for correlation between the critical logic path on the chip and the measured flush time through a known length SRL chain on the same chip. A string of data bits are flushed through the SRL chain for a measured period of time with all gates up to allow the data chain to flow freely (not clocked). After the measured flush time has elapsed, the SRL gates are lowered and the SRL chain is read out. The data bit string penetration into the SRL chain, i.e., the number of stages in the chain through which the lead bit moved during the elapsed time, is detected. The measured flush time is shortened on each successive test pass until the flush fails to progress through the entire SRL chain. Once the measured flush time has been established for a particular chip design, a cross section of the same product is tested to verify a consistent fail pattern. This is necessary for a reliable test to be used in manufacturing for product performance measurements. A fail must occur during this test to es...