Browse Prior Art Database

Process for Trench Planarization

IP.com Disclosure Number: IPCOM000061547D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Chiu, TY: AUTHOR [+2]

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to a method of planarizing refilled isolation or storage capacitor trenches. Improved etching control of refilled trenches is obtained by establishing an oxide reference plane, since planarization is in dependent of non-uniformity in both trench etching and amount of refilled material. This process is applicable to trenches refilled with either polysilicon or epitaxial silicon. Referring to Fig. 1 and the process for leveling polysilicon, a silicon wafer 1 having a recess oxide layer 2 has deposited thereon layers of nitride 3, oxide 4, nitride 5, oxide 6 and polysilicon 7. Low pressure chemical vapor deposition is used for the nitride layers 3 and 5 while conventional chemical vapor deposition is used for the oxide and polysilicon layers.

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Process for Trench Planarization

This article relates generally to integrated circuit fabrication and, more particularly, to a method of planarizing refilled isolation or storage capacitor trenches. Improved etching control of refilled trenches is obtained by establishing an oxide reference plane, since planarization is in dependent of non-uniformity in both trench etching and amount of refilled material. This process is applicable to trenches refilled with either polysilicon or epitaxial silicon. Referring to Fig. 1 and the process for leveling polysilicon, a silicon wafer 1 having a recess oxide layer 2 has deposited thereon layers of nitride 3, oxide 4, nitride 5, oxide 6 and polysilicon 7. Low pressure chemical vapor deposition is used for the nitride layers 3 and 5 while conventional chemical vapor deposition is used for the oxide and polysilicon layers. Photoresist is applied to lithographically expose the trench location 8, and reactive ion etching (RIE) is used to remove a portion of polysilicon layer 7. Upon subsequent removal of the resist, the remainder of polysilicon layer 7 serves as a mask for reactive ion etching of layers 2, 3, 4, 5 and 6. Thereafter, remaining trench etching of wafer 1 is done by RIE and thermal oxide layer 10 is formed, as shown in Fig. 2. Nitride layer 11 is deposited by low pressure chemical vapor deposition, and the trench is filled with polysilicon 12. Photoresist 13 is added over the trench, and surrounding polysilicon 12 a...