Browse Prior Art Database

Driver With Noise-Dependent Switching Speed Control

IP.com Disclosure Number: IPCOM000061548D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Frasch, G: AUTHOR [+5]

Abstract

Driver T1, T2 is provided with an additional sense circuit T3, T4 controlled by the noise voltage peeks on ground line GND. Circuit T3, T4 controls a control circuit T5, T6 which is arranged parallel to the driver output OUT and which optimally sets the driver switching speed, depending on the sensed noise voltage. The trend of VLSI microprocessor development has been towards larger chips, wider on-chip buses, higher performance, and faster clocks. Wider buses, however, require a larger number of internal on-chip tristate drivers. As such drivers often drive relatively high capacitive loads, a high current, directly proportional to the switching speed, flows for a short time during logic state switching, leading to voltage peeks on the power and ground lines of the chip.

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Driver With Noise-Dependent Switching Speed Control

Driver T1, T2 is provided with an additional sense circuit T3, T4 controlled by the noise voltage peeks on ground line GND. Circuit T3, T4 controls a control circuit T5, T6 which is arranged parallel to the driver output OUT and which optimally sets the driver switching speed, depending on the sensed noise voltage. The trend of VLSI microprocessor development has been towards larger chips, wider on-chip buses, higher performance, and faster clocks. Wider buses, however, require a larger number of internal on-chip tristate drivers. As such drivers often drive relatively high capacitive loads, a high current, directly proportional to the switching speed, flows for a short time during logic state switching, leading to voltage peeks on the power and ground lines of the chip. These voltage peeks may be of such magnitude, particularly if a larger number of drivers switch simultaneously, that the unselected receivers at the other end of the bus are erroneously switched. As the voltage peeks are proportional to the switching speed, state-of-the-art drivers have been designed for lower speeds than those technically feasible. The drawing shows a driver with optimized switching characteristics. The driver invariably operates as fast as the respective circumstances permit. Slower drivers, which have been necessary for simultaneous switching and to compensate for process tolerances, are no longer required. The actual driver consists of a FET T1 series-connected to a complementary FET T2 between supply voltage V and ground. Input IN of the driver is formed by the two gates of T1 and T2 and output OUT by the common node. Ground line GND is connected to the gate of a sense FET T3 which, series-connected...