Browse Prior Art Database

Six Square Read-Only Storage Cell

IP.com Disclosure Number: IPCOM000061550D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

This article shows a read-only storage (ROS) cell layout using two by three (6 square) layout ground rules and where multilevel voltage signals are generated on a bit line. The cell structure achieves its small layout area by sharing each metal-to-diffusion contact with four devices or cells. A six square layout is shown in the figure. Word lines (WL 0 and WL 1) are polysilicon. Bit lines (BL 0 and BL 1), power rail (VLL) and ground lines (GND) are metal. Each cell is personalized by the presence or absence of recessed oxide (ROX) under a polysilicon word line between the adjacent bit line and ground rail (cell 1) or adjacent bit line and power rail VLL (cell 2). ROS cells are personalized utilizing one ROX mask.

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Six Square Read-Only Storage Cell

This article shows a read-only storage (ROS) cell layout using two by three (6 square) layout ground rules and where multilevel voltage signals are generated on a bit line. The cell structure achieves its small layout area by sharing each metal-to-diffusion contact with four devices or cells. A six square layout is shown in the figure. Word lines (WL 0 and WL 1) are polysilicon. Bit lines (BL 0 and BL
1), power rail (VLL) and ground lines (GND) are metal. Each cell is personalized by the presence or absence of recessed oxide (ROX) under a polysilicon word line between the adjacent bit line and ground rail (cell 1) or adjacent bit line and power rail VLL (cell 2). ROS cells are personalized utilizing one ROX mask. Because two cells are located at the intersection of each word line and bit line, a multilevel sense signal is provided depending on whether one device, two devices or no devices are personalized at an intersection. Several methods of operation are possible; however, the method described is most easily implemented with conventional integrated chip technologies. Assuming n- channel storage devices (cells 1 and 2), the bit lines are initially charged to a potential higher than VLL and word lines are grounded. If no devices are personalized, the bit line potential remains high when a word line is selected. If one device is personalized between either the bit line and VLL (cell 2) or the bit line and GND (cell 1), then the b...