Browse Prior Art Database

Low Power BIFET Circuit

IP.com Disclosure Number: IPCOM000061563D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Klimanis, VD: AUTHOR [+3]

Abstract

A design has been proposed that uses N metal oxide semiconductor (NMOS) and PMOS devices instead of resistive loads in a logic circuit. The combination of field-effect transistor (FET) and bipolar devices can produce a high speed logic inverter with very high input impedance, high current sink capability, active pullup and zero power dissipation in the off state. The low power BIFET (LPB) circuit shown in the drawing uses PFETs connected as source followers to provide a NAND logic function followed by a bipolar inverter with NFETs to supply the base drive and PFET, collector pullup devices. The PFETs T3 and T4 are used as source-follower logic gates which provide very high input impedance and which do not require current sinking by the driving circuit. The base current for the bipolar transistor is provided by NFETs T1 and T2.

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Low Power BIFET Circuit

A design has been proposed that uses N metal oxide semiconductor (NMOS) and PMOS devices instead of resistive loads in a logic circuit. The combination of field-effect transistor (FET) and bipolar devices can produce a high speed logic inverter with very high input impedance, high current sink capability, active pullup and zero power dissipation in the off state. The low power BIFET (LPB) circuit shown in the drawing uses PFETs connected as source followers to provide a NAND logic function followed by a bipolar inverter with NFETs to supply the base drive and PFET, collector pullup devices. The PFETs T3 and T4 are used as source-follower logic gates which provide very high input impedance and which do not require current sinking by the driving circuit. The base current for the bipolar transistor is provided by NFETs T1 and T2. They are used as source followers and connected in series to supply base drive only when both inputs are up. The source terminals of PFETs T3 and T4 are connected to the base of bipolar transistor T7. Their drain terminals are grounded, and their gate terminals are connected to the input nodes. When either input 1 or 2 is down or 1 and 2 together are down, the gate-source of T3 or T4 or T3 and T4 is forward biased. Drain-source conduction occurs, and T7 is turned off. With both inputs up, T7 is on and PFETs T5 and T6 are off. The latter two are used instead of the usual collector pullup resistor. Their gates are conn...