Browse Prior Art Database

Image-Reduction Circuit

IP.com Disclosure Number: IPCOM000061564D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Shinzoh, N: AUTHOR

Abstract

This image-reduction circuit includes a shift register into which a bit pattern representing the image-reduction ratio is set, and a control circuit for responding to the bit pattern to control the selective extract ion of the data bits of the original image to form the reduced image. Fig. 1 shows the original image 1 of 8 x 8 pels (picture elements) which is stored in a display buffer (not shown), a vertically reduced image 2 with a reduction ratio of 3/8, and a horizontally reduced image 3 with a reduction ratio of 3/8 which is supplied to the display screen (not shown). Pel lines A, D and G are extracted to form the image 2, and columns a, d and g are extracted to form the image 3 with the total reduction ratio of 9/64. Fig. 2 shows the circuit for vertically reducing the original image 1 to form the image 2.

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Image-Reduction Circuit

This image-reduction circuit includes a shift register into which a bit pattern representing the image-reduction ratio is set, and a control circuit for responding to the bit pattern to control the selective extract ion of the data bits of the original image to form the reduced image. Fig. 1 shows the original image 1 of 8 x 8 pels (picture elements) which is stored in a display buffer (not shown), a vertically reduced image 2 with a reduction ratio of 3/8, and a horizontally reduced image 3 with a reduction ratio of 3/8 which is supplied to the display screen (not shown). Pel lines A, D and G are extracted to form the image 2, and columns a, d and g are extracted to form the image 3 with the total reduction ratio of 9/64. Fig. 2 shows the circuit for vertically reducing the original image 1 to form the image 2. Start column address a is set in column counter 4 at the start of read operation for each pel line. The column counter 4 is advanced by a column address advance clock, whereby the column counter 4 sequentially generates the column addresses a, b, ..., f, g, h. Line counter 5 sequentially generates the selective line addresses A, D and G under the control of counter control 6 and eight- bit rotating shift register 7. The following bit pattern for the 3/8 reduction is set in the shift register 7. 10110110 Start pulse and clock pulse are applied to the counter control 6, which advances the line counter 5 and shifts the shift register 7 by one position. The line counter 5 points the line address B and the bit pattern in the shift register 7 becomes: 01011011 The rightmost bit "1" is applied to the counter control 6. The counter control 6 gates the clock pulse to the line counter 5 and shif...