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LSSD Testable Four-Port Register

IP.com Disclosure Number: IPCOM000061568D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Donze, RL: AUTHOR [+4]

Abstract

Many computer systems have data flow logic implemented with level sensitive scan design (LSSD) which is testable in a manner set forth in U. S. Patent 4,268,902. The 4-port register designed using LSSD is not only testable but offers a density advantage over standard TTL (transistor-transistor logic) latches. The register has two input and two output ports which can operate simultaneously. The register bank (Fig. 3) is constructed in the following manner: . L1 latches (standard polarity hold L1 latches) are used to construct two 18-bit registers. . The +L1 output of one of these registers is used to drive the port1 data input of the register bank, and the +L1 output of the other L1 register is used to drive the port2 data input of the register bank. .

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LSSD Testable Four-Port Register

Many computer systems have data flow logic implemented with level sensitive scan design (LSSD) which is testable in a manner set forth in U. S. Patent 4,268,902. The 4-port register designed using LSSD is not only testable but offers a density advantage over standard TTL (transistor-transistor logic) latches. The register has two input and two output ports which can operate simultaneously. The register bank (Fig. 3) is constructed in the following manner:
. L1 latches (standard polarity hold L1 latches) are used to construct two 18-bit registers. . The +L1 output of one of these registers is used to drive the port1 data input of the register bank, and the +L1 output of the other L1 register is used to drive the port2 data input of the register bank. . Words 0 and 1 of the register bank are constructed with L2* latches (polarity hold latch) (Fig. 1). . Words 2 through 15 of the register bank are constructed with L3* latches (L3 latch with both a scan and separate data port) (Fig. 2). . Two scan paths are formed between one L1 register and word 0 of the register bank, and the other L1 register and word 1 of the register bank. These may be combined into a single scan path for the chip. During system operation, the scan port of the L2* latches is used as a data port, and during testing it is used as a scan port. Since the data into the scan port of the L2* latch is always fed directly from a L1 latch, this can be accomplished by having the clock for the scan port be the logical "OR...