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Enhanced Electrostatic Discharge Buffer Network

IP.com Disclosure Number: IPCOM000061569D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Levy, JR: AUTHOR [+2]

Abstract

Superior protection of integrated circuit devices from electrostatic discharge (ESD) damage is achieved in chip layout design by the placement of an ESD buffer network in very close proximity to all chip pads. A preferred ESD buffer network includes a first voltage divider circuit having a first resistor serially connected with a thick oxide field- effect transistor (FET) with grounded gate and a second voltage divider circuit having a second resistor serially connected with a thin oxide device, one end of the second resistor being connected to a control electrode of a transistor which is to be protected. Advantage is taken of existence of parasitic bipolar devices associated with the FET devices.

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Enhanced Electrostatic Discharge Buffer Network

Superior protection of integrated circuit devices from electrostatic discharge (ESD) damage is achieved in chip layout design by the placement of an ESD buffer network in very close proximity to all chip pads. A preferred ESD buffer network includes a first voltage divider circuit having a first resistor serially connected with a thick oxide field- effect transistor (FET) with grounded gate and a second voltage divider circuit having a second resistor serially connected with a thin oxide device, one end of the second resistor being connected to a control electrode of a transistor which is to be protected. Advantage is taken of existence of parasitic bipolar devices associated with the FET devices. During a transient ESD event, the voltage developed across the FETs is clamped at the sustaining voltage of the parasitic bipolar devices. The figure contains a diagram of the preferred ESD buffer network 2, which is placed physically very close and electrically connected to chip pad 4. A first voltage divider circuit is comprised of a first resistor Rc serially connected with N+ drain diffusion d1 of the thick oxide device T1 having its gate and N+ source diffusion s1 connected to a substrate or ground bus B. The resistor Rc is of small ohmic value and actually comprised of contact resistance in connection of first level metal to an N+ contact plus collector resistance of parasitic bipolar transistor Tb1. The bus B connec...