Browse Prior Art Database

Split Emitter CTS Memory Cell

IP.com Disclosure Number: IPCOM000061574D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A small, fast memory cell type, which offers an improved access time at a higher density than that obtainable from the conventional CTS (complementary-transistor switch) cell, is described in this article. CTS-type memory cells, employed in high performance memory arrays, commonly use two groups of merged transistors (cross-coupled) to provide the flip-flop, while requiring two other devices for Read-Write coupling. These Read-Write devices may be eliminated by employing the split emitters of the flip-flop to accomplish the Read-Write couplings, with benefit to cell density (reduced cell size). The disclosed split emitter complementary-transistor switch (SECTS) cell circuit and an accompanying cell layout sketch are shown in Fig. 1, where the transistor emitter, collector and base are respectively identified by E,C and B. Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Split Emitter CTS Memory Cell

A small, fast memory cell type, which offers an improved access time at a higher density than that obtainable from the conventional CTS (complementary- transistor switch) cell, is described in this article. CTS-type memory cells, employed in high performance memory arrays, commonly use two groups of merged transistors (cross-coupled) to provide the flip-flop, while requiring two other devices for Read-Write coupling. These Read-Write devices may be eliminated by employing the split emitters of the flip-flop to accomplish the Read- Write couplings, with benefit to cell density (reduced cell size). The disclosed split emitter complementary-transistor switch (SECTS) cell circuit and an accompanying cell layout sketch are shown in Fig. 1, where the transistor emitter, collector and base are respectively identified by E,C and B. Fig. 2 illustrates an array organization featuring SECTS cells, and Fig. 3 shows a SECTS cell arrangement with common Read-Write devices. In Fig. 2, the array consists of 256 rows by 160 columns in a 4K by 10 organization, where N = 256, L = 160, M = 16 and K = 10. Note: Bit selects for Read and Write may be combined. In Fig. 3, the array consists of 256 rows by 160 columns, where L = 160, M = 16 and N = 16. Note: Bit segments are connected at the device level with the N+ polysilicide available in the transistor emitter structure, as previously disclosed in the IBM Technical Disclosure Bulletin 29, 722-724 (July 1986). Operations of the disclo...