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Bus Architecture for Passive Fault-Tolerant Command/Response System

IP.com Disclosure Number: IPCOM000061575D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Balliet, L: AUTHOR [+3]

Abstract

This article describes a system arrangement which automatically circumvents and isolates single point faults without action by a controller. The low cost and programmability of microprocessor-based hardware has made multi-unit federated systems feasible and attractive. Such systems, for example, are used extensively in high volume production automobiles to interconnect units for engine control, body control, display, temperature, entertainment and other functions. In such applications, serviceability and availability are very important and it is consequently desirable to detect and isolate electronic component faults quickly while maintaining a functioning system.

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Bus Architecture for Passive Fault-Tolerant Command/Response System

This article describes a system arrangement which automatically circumvents and isolates single point faults without action by a controller. The low cost and programmability of microprocessor-based hardware has made multi-unit federated systems feasible and attractive. Such systems, for example, are used extensively in high volume production automobiles to interconnect units for engine control, body control, display, temperature, entertainment and other functions. In such applications, serviceability and availability are very important and it is consequently desirable to detect and isolate electronic component faults quickly while maintaining a functioning system. A dual ring architecture is disclosed herein in which both links are simultaneously active transferring redundant data in opposite directions around the ring network, thus producing inherent fault recovery without action by a controller. This architecture permits upgrading party line units into a high rate dual bus system. Multipoint/command response serial bus architecture is commonly implemented by microprocessor chips commercially available. A typical system, as illustrated in Fig. 1, has a serial bus interconnected via transmitters and receivers connected to a common wire or wire pair. Bus protocol is determined by an integrated circuit universal asynchronous receiver transmitter (UART) or microcomputers that have a built-in UART function. Fig. 2 shows the organization of the dual ring command/response system. As is the case in Fig. 1, the system consists of N units with one of the units programmed as the controller 1. Each unit contains one or two types of ring interface modules (RIMs) 2 or 3 that provides the interface to the dual bus 4. The two buses, labeled A and B, are unidirectional, passing data in opposite directions. Fig. 3 shows the organization of a RIM (type 1) which contains port A logic 5, port B logic 6, a logic switch 7 and a microprocessor control function 8.

Data normally passes through the logic switch when the unit is not transmitting. The microprocessor need not be functionally dedicated to the RIM. Type 1 RIMs represent the configuration for units specifically designed for the architecture. It interfaces with the parallel bus of the microprocessor. Fig. 4 shows RIM (type 2) with an independent port 9 along with other functions common to type 1 RIMs. Type 2 RIMs are independent units that adapt equipment already designed for a party line system into a dual ring system. Transfer to and from port C can be at a data rate different from ports A and
B. For example, port C can operate at 9600 bits per second, whereas data transfer over the dual ring bus would be at 50K bits per second. Bus Operation is as follows: 1. Data flow over the dual ring bus is initiated by the controller which uses conventional command/response techniques and protocol. Slave units only transmit when requested...