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Memory Cells With Resistor Clamps

IP.com Disclosure Number: IPCOM000061578D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

This article suggests the use of an inverse transistor clamp to prevent deep saturation of memory cells in semiconductor devices. When clamped, the cells will operate in pseudo-saturation mode with cell stability improved. Bipolar random-access memory (RAM) cells with Schottky barrier diode (SBD) clamps are sensitive to a-particle disturbs. If the clamps are removed to enhance the a-particle related stability, the ON transistor goes into saturation. This saturated condition results in a slower write time and bigger write time tolerance. A beta lowering implant used to improve the write performance requires an extra process step, and read access may be slowed.

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Memory Cells With Resistor Clamps

This article suggests the use of an inverse transistor clamp to prevent deep saturation of memory cells in semiconductor devices. When clamped, the cells will operate in pseudo-saturation mode with cell stability improved. Bipolar random-access memory (RAM) cells with Schottky barrier diode (SBD) clamps are sensitive to a-particle disturbs. If the clamps are removed to enhance the a- particle related stability, the ON transistor goes into saturation. This saturated condition results in a slower write time and bigger write time tolerance. A beta lowering implant used to improve the write performance requires an extra process step, and read access may be slowed. This proposal suggests the use of transistor clamps with the memory cells to provide both reasonable write performance and reasonable stability against a-particle disturbs. Transistor clamps for three different cell types are shown in the drawing. In place of conventional SBD clamps, TX and TY in the inverse mode provide a current path for the excess carriers injected into the high node of the cell. This prevents deep saturation of the flip-flop transistors T1 and T2. The VCE of the ON transistor is about 50 mV if TX or TY is the same size as T1 and T2. The degree of saturation may be adjusted with different transistor sizes to meet the specific requirements of write performance and a-stability. This scheme provides a simpler and more flexible solution to the limitations of...