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Browse Prior Art Database

CMOS Schmitt Trigger Buffer

IP.com Disclosure Number: IPCOM000061590D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Bernstein, K: AUTHOR

Abstract

The circuit discussed provides a low power, high performance CMOS buffer/driver which exhibits hysteresis and noise immunity characteristics. A dramatic gain in CMOS logic performance has been due in part to smaller stage-to-stage delays, reduced capacitive loading on terminal nodes and more versatility allowed by the CMOS technology. It is also true that noise in the signal may quickly penetrate deep into the logic design and the noise amplitude and duration is a larger percentage of the CMOS technology's shorter pulses. A CMOS circuit is shown in Fig. 1 which can be used as a buffer, receiver, predriver or sense amplifier. The circuit is effective against noise through the use of the Schmitt trigger hysteresis effect and can be tailored by the circuit designer.

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CMOS Schmitt Trigger Buffer

The circuit discussed provides a low power, high performance CMOS buffer/driver which exhibits hysteresis and noise immunity characteristics. A dramatic gain in CMOS logic performance has been due in part to smaller stage- to-stage delays, reduced capacitive loading on terminal nodes and more versatility allowed by the CMOS technology. It is also true that noise in the signal may quickly penetrate deep into the logic design and the noise amplitude and duration is a larger percentage of the CMOS technology's shorter pulses. A CMOS circuit is shown in Fig. 1 which can be used as a buffer, receiver, predriver or sense amplifier. The circuit is effective against noise through the use of the Schmitt trigger hysteresis effect and can be tailored by the circuit designer. When input A is low, at ground, N-type device N2 is off, and P- type device P1 is on hard, driving output C to +5 volts, a high output state. With device N2 off, N- type device N5 is on and in saturation, shorting the drain of N-type device N3 to its gate. Device N3 now acts as a current-limited diode and node D stays at a voltage of about +1 volt (+1 enhancement threshold). This voltage on node D acts to further turn off device N2 by reducing its gate-to-source bias. When the input A goes high (+5 volts), device P1 shuts off and device N2 turns on, shorting the gate of device N5 to its source. With the gate-to-source voltage (VGS) equal to zero, device N5 shuts off. Device N...