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CMOS Latch Circuit

IP.com Disclosure Number: IPCOM000061591D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Erdelyi, CK: AUTHOR [+2]

Abstract

A complementary metal oxide silicon (CMOS) latch circuit is described which internally opens and closes the feedback path and assures the down level, or "hold 0", condition. A high circuit density is realized, since connections and wiring to external feedback control circuitry are not required. In the figure, the basic latch circuit is formed by transistors T6, T7, T8, and T9. The feedback is through transistors T3 and T4. The latch is written through the transfer gates T1 and T2 from terminals D1 and D2, respectively, by taking set pulse C1 or C2 high, which simultaneously breaks the feedback path by turning off transistor T3 or T4. Breaking the feedback path makes the latch easier to write. When holding data, transistors T3 and T4 can maintain a good up level, but a down level or zero could be degraded.

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CMOS Latch Circuit

A complementary metal oxide silicon (CMOS) latch circuit is described which internally opens and closes the feedback path and assures the down level, or "hold 0", condition. A high circuit density is realized, since connections and wiring to external feedback control circuitry are not required. In the figure, the basic latch circuit is formed by transistors T6, T7, T8, and T9. The feedback is through transistors T3 and T4. The latch is written through the transfer gates T1 and T2 from terminals D1 and D2, respectively, by taking set pulse C1 or C2 high, which simultaneously breaks the feedback path by turning off transistor T3 or T4. Breaking the feedback path makes the latch easier to write. When holding data, transistors T3 and T4 can maintain a good up level, but a down level or zero could be degraded. Node A could float up to the P-channel threshold (Vtp). Transistor T5 serves to prevent this zero level degradation. When nodes A and C are at zero, node B is high and transistor T5 is on, which holds node A to a low level.

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