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Interchip Arbitration Design

IP.com Disclosure Number: IPCOM000061603D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Sanders, SJ: AUTHOR

Abstract

This article describes an interchip arbitration arrangement which does arbitration with rotating priority and includes a look-ahead feature that permits very fast arbitration to be achieved using a small number of chip pins. A simple arbitration design is disclosed herein which can be used to minimize input/output (I/O) requirements while maximizing performance. It can be used for arbitration among a set of chips of variable size. A unique feature of the design is its arbitration look-ahead, which permits a fast arbitration decision to be made in an otherwise serial-type design. This arrangement makes use of the best points of two types of arbitration wherein pin requirements are comparable to serial arbitration designs, and speed is comparable to that of parallel arbitration designs.

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Interchip Arbitration Design

This article describes an interchip arbitration arrangement which does arbitration with rotating priority and includes a look-ahead feature that permits very fast arbitration to be achieved using a small number of chip pins. A simple arbitration design is disclosed herein which can be used to minimize input/output (I/O) requirements while maximizing performance. It can be used for arbitration among a set of chips of variable size. A unique feature of the design is its arbitration look-ahead, which permits a fast arbitration decision to be made in an otherwise serial-type design. This arrangement makes use of the best points of two types of arbitration wherein pin requirements are comparable to serial arbitration designs, and speed is comparable to that of parallel arbitration designs. The pin requirements are as follows: - POINTER: For a set of "x" chips, a pointer of bit width n is required, where n is the smallest number for which the equation 2 n= > x holds (i.e., for 7 chips, 2 3 > 7, so 3 pins are required.) The POINTER is driven by only one chip. - HOLD: One tri-state signal is required to inform all chips when one of them has won the arbitration. - CLAIM: One tri- state signal is required to inform all chips when one of them has claimed to be the next owner of the bus, and will activate HOLD as soon as the current user has deactivated it. A set of x chips can be described as A0, A1, A2, ..., Ax-1. One of the chips is declared to be the master of the arbitration. For this example, let A0 be master of arbitration. Chip A0 is responsible for driving the POINTER to each of the other chips in the following manner: The POINTER is incremented after a given time period called a cycle. The POINTER's value is rotated, so that it follows the pattern (0, 1, 2, ..., x-1, 0, 1, 2, ...). For this example, let x = 4, so that the; rotation of the POINTER follows the sequence (0, 1, 2, 3, 0, 1, 2, 3, Fig. 1 is a diagram of the exemplary...