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Low Contact Resistance, Self-Aligned Metal Stud Process

IP.com Disclosure Number: IPCOM000061604D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Abernathy, JR: AUTHOR [+2]

Abstract

A process is described for making low resistance metal interconnections (studs) through via holes in insulator films of varying thickness. The process requires no masking steps and is performed in situ in a single "deposition and etch" tool. The top surface of the stud is very nearly co-planar with the insulator surface, regardless of the insulator film thickness. Since the top surface of the studs is metal silicide or silicon dioxide, contact resistance to a next level of standard metal wiring, e.g., aluminum (Al) or aluminum alloys, is minimized by standard Al predeposition removal of the silicon dioxide that forms. Metal oxides are created if the metal films (deposited at > than oxidation temperature) are exposed to air while hot.

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Low Contact Resistance, Self-Aligned Metal Stud Process

A process is described for making low resistance metal interconnections (studs) through via holes in insulator films of varying thickness. The process requires no masking steps and is performed in situ in a single "deposition and etch" tool. The top surface of the stud is very nearly co-planar with the insulator surface, regardless of the insulator film thickness. Since the top surface of the studs is metal silicide or silicon dioxide, contact resistance to a next level of standard metal wiring, e.g., aluminum (Al) or aluminum alloys, is minimized by standard Al predeposition removal of the silicon dioxide that forms. Metal oxides are created if the metal films (deposited at > than oxidation temperature) are exposed to air while hot. Typically, cooling the metal films (under the vacuum deposition conditions) prior to air exposure takes long periods of time and is thus not feasible for most manufacturing applications. Metal oxides are difficult to remove if formed, but formation can be eliminated through the use of a metal silicide or silicon dioxide top surface. By forming all the via holes such that they have at least one dimension of equal size D, all the holes are completely filled when the thickness of the conformal deposition equals 1/2 D, even if the insulator varies in thickness. All the via holes 16 are etched through all the insulator levels 4, 6 and 8 to expose a doped contact 14 or polysilicon lin...