Browse Prior Art Database

"Non-Fowl Mouth" Symmetric Transistor

IP.com Disclosure Number: IPCOM000061605D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Galli, CA: AUTHOR [+3]

Abstract

Disclosed is a process which eliminates the "bird's beak" at the perimeter of the emitter/base junction in semiconductor devices. The process employs a double sidewall structure to retain a Si3N4/SiO2 plug which serves as the dielectric spacer providing the isolation between the emitter and the base. In symmetric transistor fabrication using previous methods, there has been a problem with the formation of an oxidation bird's beak near the perimeter of the emitter-base junction. This is normally an uncontrollable process step in the transistor fabrication and is a potential source of parameter variability. The present process eliminates the bird's beak completely. In the process, a thin layer of SiO2, designated as 2 in Fig. 1, is grown upon the Si substrate 1.

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"Non-Fowl Mouth" Symmetric Transistor

Disclosed is a process which eliminates the "bird's beak" at the perimeter of the emitter/base junction in semiconductor devices. The process employs a double sidewall structure to retain a Si3N4/SiO2 plug which serves as the dielectric spacer providing the isolation between the emitter and the base. In symmetric transistor fabrication using previous methods, there has been a problem with the formation of an oxidation bird's beak near the perimeter of the emitter-base junction. This is normally an uncontrollable process step in the transistor fabrication and is a potential source of parameter variability. The present process eliminates the bird's beak completely. In the process, a thin layer of SiO2, designated as 2 in Fig. 1, is grown upon the Si substrate 1. A thick layer of Si3N4 3 is deposited, and then the Si is reactive ion etched (RIE). A second thin oxide layer 4 is grown, and a boron link-up implant 5 is made. A second layer of nitride is deposited, and by RIE the sidewall nitride 6, as in Fig. 2, is achieved. In this and all subsequent figures only the right side of the structure is shown since it is symmetrical. A third RIE is done with an etch rate ratio (ERR) of Si:Si3N4 of
2.5:1. The height of the nitride is adjusted for different ERRs. A slight etch of the Si is done to enhance the rounding of the corner 7 (Fig. 3) for stress reduction. A reoxidation step provides a third layer of oxide 8. A third nitride 9 dep...