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Enhanced Hashed Prefetch Confirmation

IP.com Disclosure Number: IPCOM000061612D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

Accuracy of confirmed prefetching schemes is improved by marking lines that should cause sequential prefetching in a more timely manner and avoiding collisions in a hashed table of confirmation bits. It is assumed herein that confirmed prefetching is accomplished by using some subset of the line address to determine which entry in the confirmation bit table corresponds to a given line. In this type of confirmed prefetching scheme, more than one line in memory corresponds to each confirmation bit in the table. It has been observed that the most often missed lines for a given cache configuration are those that have been most recently replaced from the cache.

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Enhanced Hashed Prefetch Confirmation

Accuracy of confirmed prefetching schemes is improved by marking lines that should cause sequential prefetching in a more timely manner and avoiding collisions in a hashed table of confirmation bits. It is assumed herein that confirmed prefetching is accomplished by using some subset of the line address to determine which entry in the confirmation bit table corresponds to a given line. In this type of confirmed prefetching scheme, more than one line in memory corresponds to each confirmation bit in the table. It has been observed that the most often missed lines for a given cache configuration are those that have been most recently replaced from the cache. Therefore, the prefetching performance will be improved if each confirmation bit is more likely to correspond to the appropriate action (prefetch next sequential or not) for lines that have been recently replaced from the cache than for any other lines that share the confirmation bit. The present scheme adds a bit per line (Successful Prefetch Bit) in the cache directory which is set to indicate that a line was successfully prefetched into the cache. By "successfully prefetched," we mean that the line was both 1. prefetched from the memory (or L2 cache, if any) by the appropriate prefetching mechanism, and 2. subsequently referenced by the processor (this indication may be provided by different mechanisms in different prefetching strategies). When a prefetch is performed, t...