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Browse Prior Art Database

Self-Aligned Electrical Connection to Trench

IP.com Disclosure Number: IPCOM000061615D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Machesney, B: AUTHOR [+2]

Abstract

A method is described to provide a self-aligned electrical connection between an insulated trench filled with highly doped polycrystalline silicon and a nearby doped silicon region. Referring to Fig. 1, a trench 2 is formed in a silicon substrate 4 by defining an opening having a width W in photoresist 8, and reactive ion etching (RIE) the exposed silicon after an isotropic etch removal of SiO2 layer 6. The isotropic etch time is extended to create an opening in the SiO2 wider than the photoresist opening W, as shown. Photoresist 8 is then removed, and, as shown in Fig. 2, insulating layer 10 is formed. Highly doped polycrystalline silicon 14 is next deposited conformally by chemical vapor deposition (CVD) to over-fill the trench to a level indicated by the dashed line 12.

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Self-Aligned Electrical Connection to Trench

A method is described to provide a self-aligned electrical connection between an insulated trench filled with highly doped polycrystalline silicon and a nearby doped silicon region. Referring to Fig. 1, a trench 2 is formed in a silicon substrate 4 by defining an opening having a width W in photoresist 8, and reactive ion etching (RIE) the exposed silicon after an isotropic etch removal of SiO2 layer 6. The isotropic etch time is extended to create an opening in the SiO2 wider than the photoresist opening W, as shown. Photoresist 8 is then removed, and, as shown in Fig. 2, insulating layer 10 is formed. Highly doped polycrystalline silicon 14 is next deposited conformally by chemical vapor deposition (CVD) to over-fill the trench to a level indicated by the dashed line 12. A planarization etch is used to remove the silicon 14 to a level slightly below the SiO2 layer 6 top surface, as shown. After region 16 (Fig. 3) is formed by ion implantation, a layer 18 of refractory metal is deposited over the entire surface to a level indicated by dashed line 20. Annealing then reacts silicon and the refractory metal where the two elements are in contact, to form a conductive silicide 22. Unreacted refractory metal is removed by a selective etch. Thus, interconnection of the highly doped polycrystalline silicon 14 in the trench and the nearby doped silicon region 16 is accomplished by silicide bridge 22.

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