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Multi-Port Serial Communications Controller With Dual-Port RAM Interface

IP.com Disclosure Number: IPCOM000061620D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Caraballo, MP: AUTHOR [+5]

Abstract

A technique is described whereby a multi-port serial communications controller, equipped with a dual-port random-access memory (RAM) interface, increases data throughput to attachments, such as terminals, printers, and other communication devices, as well as increasing throughput to other interconnected systems. The concept is unique in that the controller allows all terminal ports connected to the attachments to operate simultaneously. A microcontroller is utilized to keep track of which port is active while controlling the placement of data within the RAM. Only a single system interrupt is used, and the concept does not require the use of a data memory access (DMA) channel to a host system. In prior art, a single communication line was controlled per attachment adapter.

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Multi-Port Serial Communications Controller With Dual-Port RAM Interface

A technique is described whereby a multi-port serial communications controller, equipped with a dual-port random-access memory (RAM) interface, increases data throughput to attachments, such as terminals, printers, and other communication devices, as well as increasing throughput to other interconnected systems. The concept is unique in that the controller allows all terminal ports connected to the attachments to operate simultaneously. A microcontroller is utilized to keep track of which port is active while controlling the placement of data within the RAM. Only a single system interrupt is used, and the concept does not require the use of a data memory access (DMA) channel to a host system. In prior art, a single communication line was controlled per attachment adapter. Also, a single interrupt and/or DMA channel was required for each adapter. The technique described herein allows multiple communication lines to be attached to an adapter and reduces the number of interrupts that would be in contention for the host system's channel. When a byte of data is received to any one of the ports A to G, as shown in the figure, an interrupt is signalled to microcontroller 10 so it can read the data on data path 11. Arbiter 12 resolves any contention when both microcontroller 10 and the host system requests access to the dual-port RAM 13 simultaneously. Data is written into dual-port RAM 13 in blocks of 256 bytes. Once a 256-byte block is filled, microcontroller 10 interrupts system processor 14 to signal that a block of data is available for processing. System processor 14 will then read th...