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Reworkable Chip-On-Board Package

IP.com Disclosure Number: IPCOM000061621D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Gons, S: AUTHOR

Abstract

This article describes a technique which will allow one rework cycle per chip site when a chip-on-board package is utilized. Back bonded chip-on-board packages are difficult to replace when defective chips must be replaced and the rework may cause damage to the surrounding area. In order to improve board yields, a technique which allows one rework cycle per chip site is shown. Fig. 1 shows the cross-section of a two-layer board 10 on substrate 11, comprised of a central ground plane 12 and a top layer 13 with board pads 14 thereon. Chip pockets 15 are milled through the top layer 13 of the board 10 to expose ground plane 12. Before a chip 16 is back bonded, in chip pocket 15, to ground plane 12 with an epoxy 17, the exposed ground plane 12 may be plated with nickel and gold (not shown).

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Reworkable Chip-On-Board Package

This article describes a technique which will allow one rework cycle per chip site when a chip-on-board package is utilized. Back bonded chip-on-board packages are difficult to replace when defective chips must be replaced and the rework may cause damage to the surrounding area. In order to improve board yields, a technique which allows one rework cycle per chip site is shown. Fig. 1 shows the cross-section of a two-layer board 10 on substrate 11, comprised of a central ground plane 12 and a top layer 13 with board pads 14 thereon. Chip pockets 15 are milled through the top layer 13 of the board 10 to expose ground plane 12. Before a chip 16 is back bonded, in chip pocket 15, to ground plane 12 with an epoxy 17, the exposed ground plane 12 may be plated with nickel and gold (not shown). After chip 16 is back bonded in place, chip pads 18 are wire bonded to board pads 14. When a chip site, as shown in Fig. 2a, is to be reworked, the wire bonds between pads 14 and 18 on chip 16 are removed and a replacement chip 19 is back bonded with epoxy 20 to the top of defective chip 16. Wire bonds between pads 14 and 18 on chip 19 are restored. Fig. 2b shows the replacement chip 19 bonded to the top of defective chip 16 with electrically conductive epoxy
20. When electrical contact between ground and chip must be maintained, epoxy is applied in such a manner as to contact the original grounded back bond epoxy
17. Another option is to design in...