Browse Prior Art Database

Direct, Asynchronous and Synchronous Storage Card

IP.com Disclosure Number: IPCOM000061627D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Bannon, RD: AUTHOR [+4]

Abstract

This article describes an arrangement wherein direct, asynchronous and synchronous operations are serviced, buffered and reconciled on a two- port storage card design. Existing technology is available to solve the problem of sharing dynamic, high density, low cost storage with synchronous CPU operation and asynchronous I/O operation. The direct asynchronous and synchronous storage card (DASSC) is a two-port card (CPU port and I/O port), that also includes facilities for direct CPU to I/O communication not utilizing the storage. Thus, three basic lines of communication are solved by this two-port design. Fig. 1 illustrates the entire DASSC operation. A 43-line storage control unit (SCU) interfaces the storage card.

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Direct, Asynchronous and Synchronous Storage Card

This article describes an arrangement wherein direct, asynchronous and synchronous operations are serviced, buffered and reconciled on a two- port storage card design. Existing technology is available to solve the problem of sharing dynamic, high density, low cost storage with synchronous CPU operation and asynchronous I/O operation. The direct asynchronous and synchronous storage card (DASSC) is a two-port card (CPU port and I/O port), that also includes facilities for direct CPU to I/O communication not utilizing the storage. Thus, three basic lines of communication are solved by this two-port design. Fig. 1 illustrates the entire DASSC operation. A 43-line storage control unit (SCU) interfaces the storage card. The lines would typically consist of 36 bits (32 address or data plus 4 parity); RSEL (read select); WSEL (write select); STGRDY (storage ready); MSCLK (main store clock); MSOE (main store output enable); and two status lines. The SCU interface on the DASSC would also contain a storage address register; a 16-byte line buffer; parity generation checking and compare on a byte basis; SEC-DED (single error correct-double error detect) (shared) ECC (error checking and correction) (64 data/8 check) and finally the lines of communication with up to two megabytes of storage. Separate clocking and control reconciled by memory contention circuitry provides the synchronous communication that the SCU demands. A 52-line I/O bus provides the interface with the DASSC. The lines consist of 36 bits (32 address or data plus 4 parity); I/O RDY (I/O ready); A SEL (address select); D SEL (data select); WNR (write not read); 4-byte mode lines; IO NM (I/O not memory); 3 status lines; 2 reset lines; and 2 address control lines in conjunction with byte-mode operation. The I/O interface contains the following: storage address register, 16- byte line buffer, SEC (shared) DED ECC, parity and lines of communication with up to two megabytes of storage. The clocking and control circuitry determines which interface uses storage. In addition, byte-mode operation is an integral part of the asynchronous nature of I/O...