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Minimized Implementation for a Digital Data Clock Extraction and Synchronization

IP.com Disclosure Number: IPCOM000061630D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Chliwnys, A: AUTHOR [+2]

Abstract

The function consists of synchronizing data variation to a clock period. It provides the capability to synchronize "Ones" data to clock by correcting its own clock period by "1/11th" for that period, on the fly (Fig. 1). The implementation consists of an advance and retard Johnson counter. The counter samples the clock period at an odd number of intervals. In this embodiment, the sample is "11". The sample count advances or retards by one sample or "1/11th" of the clock period, with respect to "Ones" data leading or lagging. No corrections are made for "Zeros" data or when data is in sync with the clock period. The Johnson counter consists of 6 polarity hold latches or SRLs (Shift Register Latches for LSSD) Modulo 12 count (Fig. 2). NRZI data is converted into RZ data and then sampled by the counter.

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Minimized Implementation for a Digital Data Clock Extraction and Synchronization

The function consists of synchronizing data variation to a clock period. It provides the capability to synchronize "Ones" data to clock by correcting its own clock period by "1/11th" for that period, on the fly (Fig. 1). The implementation consists of an advance and retard Johnson counter. The counter samples the clock period at an odd number of intervals. In this embodiment, the sample is "11". The sample count advances or retards by one sample or "1/11th" of the clock period, with respect to "Ones" data leading or lagging. No corrections are made for "Zeros" data or when data is in sync with the clock period. The Johnson counter consists of 6 polarity hold latches or SRLs (Shift Register Latches for LSSD) Modulo 12 count (Fig. 2). NRZI data is converted into RZ data and then sampled by the counter. Detection of the "Ones" data (NRZI transition) prior to the count of "5", sets the early latch, which causes the counter to wrap after the count of "9". Detection of "Ones" data higher than the count of "5" will cause the late latch to be set, which causes the counter to wrap after the count of "11". For "Ones" data coinciding with the count of "5", and "Zeros" data the counter wraps after the count of "10" (Fig. 3). By using the Johnson counter, all the decoding logic gates, "fan in", "fan out" and logic levels were reduced to a minimal, which made it possible to use the 3 um. CMOS gate...