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Method of Supporting an Increase in the Number of Address Spaces for the IBM Series/1 Computer System

IP.com Disclosure Number: IPCOM000061637D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique is described whereby address space, as used in the IBM Series/1 (S/1) computer architecture, is increased from its limitation of eight address spaces, so as to make provision for extending the address capability of the S/1. The S/1 architecture is limited to utilizing a four-bit address space key to specify system address spaces. Each of the spaces is 64 kilobytes in size. Since S/1 is a 16-bit word system, the total system logic address is sixteen 64K-byte spaces or one megabyte. This concept provides a method of supporting more address spaces.

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Method of Supporting an Increase in the Number of Address Spaces for the IBM Series/1 Computer System

A technique is described whereby address space, as used in the IBM Series/1 (S/1) computer architecture, is increased from its limitation of eight address spaces, so as to make provision for extending the address capability of the S/1. The S/1 architecture is limited to utilizing a four-bit address space key to specify system address spaces. Each of the spaces is 64 kilobytes in size. Since S/1 is a 16-bit word system, the total system logic address is sixteen 64K-byte spaces or one megabyte. This concept provides a method of supporting more address spaces. Tied in with the increase of addresses per address space from 16 bits to 24, the method utilizes an eight-bit Space Identifier (SID), so as to support 256 unique address spaces, for a system total logical addressing capability of 32 bits instead of 20 bits in the present S/1 concept, for a total of four gigabytes.

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