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Logical to Physical Address Translation for Computer Systems With Extended Memory Addressing

IP.com Disclosure Number: IPCOM000061640D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique is described whereby an address translation mechanism translates a 32-bit logical address into a 24-bit real address. Using a Space Identifier (SID) from a Level Status Block (LSB) of the active task, an address space array is accessed to obtain the segment table origin address. This address is added to the logical segment address of the effective address to create a 13-bit physical segment address. The addresses are then concatenated and used to access the required bytes in storage. The address translation flow is shown in Fig. 1. The add function, as shown in Fig. 2, allows a segment table to be at any four-byte boundary and may be any number of entries in length. For each active address space, a segment table is generated by the system and placed in the associated segment table.

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Logical to Physical Address Translation for Computer Systems With Extended Memory Addressing

A technique is described whereby an address translation mechanism translates a 32-bit logical address into a 24-bit real address. Using a Space Identifier (SID) from a Level Status Block (LSB) of the active task, an address space array is accessed to obtain the segment table origin address. This address is added to the logical segment address of the effective address to create a 13-bit physical segment address. The addresses are then concatenated and used to access the required bytes in storage. The address translation flow is shown in Fig. 1. The add function, as shown in Fig. 2, allows a segment table to be at any four-byte boundary and may be any number of entries in length. For each active address space, a segment table is generated by the system and placed in the associated segment table. The entry contains the physical page address which correlates to the logical page address used by the software.

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