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Invalid Address Protection for Computer Systems With Extended Memory Addressing

IP.com Disclosure Number: IPCOM000061641D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique is described whereby invalid address protection provides a means of insuring that only the addresses necessary to enable extended addressing of computer programming will be implemented. A program check interrupt handler is provided in conjunction with a segment identifier to signal the following conditions: a) Invalid Effective Address bit - If bit 0 of any processor effective address is 0 and the program is running in problem state, or if bit 0 of an instruction address changes during the computation of a jump address, a program check will occur with the extended processor status word (EPSW) bits 01 and 06 set on. b) Invalid Address Space - If bit 0 in the address space array entry pointed to by an active segment identifier is off, this specifies that an invalid address space has occurred.

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Invalid Address Protection for Computer Systems With Extended Memory Addressing

A technique is described whereby invalid address protection provides a means of insuring that only the addresses necessary to enable extended addressing of computer programming will be implemented. A program check interrupt handler is provided in conjunction with a segment identifier to signal the following conditions: a) Invalid Effective Address bit - If bit 0 of any processor effective address is 0 and the program is running in problem state, or if bit 0 of an instruction address changes during the computation of a jump address, a program check will occur with the extended processor status word (EPSW) bits 01 and 06 set on. b) Invalid Address Space - If bit 0 in the address space array entry pointed to by an active segment identifier is off, this specifies that an invalid address space has occurred. When this occurs, the program check interrupt handler is activated. c) Segment Length Exceeded - Bits 8-20 of the effective address (logical segment address) contain a number which is greater than the number in bits 23-35 of the entry in the address space array pointed to by the active segment identifier. A program check will occur and the 01 bit of the EPSW will be set on, indicating an invalid storage address, and the EPSW bit 18 is set on to indicate that the segment length is exceeded. d) Segment Table Entry Address (STEA) exceeds real memory - If the real segment table entry address, resulting from the add during address translation, exceeds the amount of real memory on the system, a program check will occur. It should be noted that this exception can only...