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Non-Active Address Protection for Computer Systems With Extended Memory Addressing

IP.com Disclosure Number: IPCOM000061642D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique is described to insure that addresses, used in computer systems with extended addressing capabilities, which have not been activated by the system are protected from being accessed. In the IBM Series/1 system, which was implemented to include extended addressing (see page 1494), a potential exists that much of the total system's addressable address space would be non-active, i.e., space which has not been allocated for use. Since there are 256 possible address spaces, each of which can be allocated to be from 1 to 8K segments of 2K bytes each, the non-active addresses may be entire address spaces of segments within an address. To insure that no accesses can be made to either of these types of non-active addresses, a mechanism is provided to detect and prevent against such errors.

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Non-Active Address Protection for Computer Systems With Extended Memory Addressing

A technique is described to insure that addresses, used in computer systems with extended addressing capabilities, which have not been activated by the system are protected from being accessed. In the IBM Series/1 system, which was implemented to include extended addressing (see page 1494), a potential exists that much of the total system's addressable address space would be non- active, i.e., space which has not been allocated for use. Since there are 256 possible address spaces, each of which can be allocated to be from 1 to 8K segments of 2K bytes each, the non-active addresses may be entire address spaces of segments within an address. To insure that no accesses can be made to either of these types of non-active addresses, a mechanism is provided to detect and prevent against such errors. During address translation, an active Space Identifier (SID) is used to access 1 to 256 entries in the address space array. Bit 0 of the entry is tested. If the bit is off, the address space relating to the entry is non-active and an addressing exception interrupt is executed. If bit 0 is on, the address space is active and address translation is allowed to continue. A second check is made to establish that the segment being addressed within the address space does not exceed the active size of the address space. Bits 8 through 20 of the System Logical Address are compared to Bits 23 through 35...