Browse Prior Art Database

Translated Address Cache in Computer Systems With Extended Memory Addressing

IP.com Disclosure Number: IPCOM000061643D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique is described whereby a translated address cache is provided in computer systems with extended addressing capabilities so as to eliminate the need to access memory segment tables in determining the real page address, in addition to the required data access. The translated address cache is inserted in the memory control section of the extended addressing unit, as shown in the figure. Since the address translation algorithm (see page 1478) requires that two storage accesses be made for each instruction or operand access, the use of a cache mechanism eliminates additional accesses to storage for a high percentage of store requests. The translated address cache is unique in that it operates in parallel with the logical-to-physical address translation mechanism.

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Translated Address Cache in Computer Systems With Extended Memory Addressing

A technique is described whereby a translated address cache is provided in computer systems with extended addressing capabilities so as to eliminate the need to access memory segment tables in determining the real page address, in addition to the required data access. The translated address cache is inserted in the memory control section of the extended addressing unit, as shown in the figure. Since the address translation algorithm (see page 1478) requires that two storage accesses be made for each instruction or operand access, the use of a cache mechanism eliminates additional accesses to storage for a high percentage of store requests. The translated address cache is unique in that it operates in parallel with the logical-to-physical address translation mechanism. If the desired physical page address is in cache, then that is the address used to address main storage. If the desired physical page address is not in cache, then the address is obtained from the address translator and the segment identifier (SID) is recorded in the table directory and the address from the translator is recorded in the SID table cache. The number of entries into the cache mechanism is limited to the maximum number of segments in the address space. Each entry contains a physical segment address and the SID of the address whose logical segment address is currently mapped to the physical page addressed. Durin...