Browse Prior Art Database

Interrupts and Level Switching for Computer Systems With Extended Memory Addressing

IP.com Disclosure Number: IPCOM000061646D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique describes the way interrupts and level switching are handled when the IBM Series/1 computers are equipped with extended addressing capabilities. A system running in extended mode handles interrupts in the same way as in compatibility mode with the following differences: Address Space Selection - In compatibility mode, Address Key 0 is used to invoke the proper interrupt handler program. In extended addressing mode, one of two address spaces is chosen as a function of the type of interrupt. All I/O interrupts are vectored using system identifier (SID) zero. Class interrupts are vectored using either SID 0 or the System SID in the active extended level status block (ELSB). Determining which SID is used is a function of the specific class interrupt.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 63% of the total text.

Page 1 of 1

Interrupts and Level Switching for Computer Systems With Extended Memory Addressing

A technique describes the way interrupts and level switching are handled when the IBM Series/1 computers are equipped with extended addressing capabilities. A system running in extended mode handles interrupts in the same way as in compatibility mode with the following differences: Address Space Selection - In compatibility mode, Address Key 0 is used to invoke the proper interrupt handler program. In extended addressing mode, one of two address spaces is chosen as a function of the type of interrupt. All I/O interrupts are vectored using system identifier (SID) zero. Class interrupts are vectored using either SID 0 or the System SID in the active extended level status block (ELSB). Determining which SID is used is a function of the specific class interrupt. Addressing During Interrupt Vectoring - Although starting instruction addresses (SIAs), level status block (LSB) pointers and device description block (DDB) pointers remain allocated in lower main storage, as in compatibility mode, and therefore continue to be single words, in extended mode, the usage differs as follows: Interrupts - When loading the DDB pointer into the low-order word of register one of the interrupted level, the high-order word of the register is set to zero. The SIA is specified to be a double word as is the start instruction accessed using the SIA pointer. Bit zero of the start instruction must be zero, or...