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Input/Output Address Translation for Computer Systems With Extended Memory Addressing

IP.com Disclosure Number: IPCOM000061647D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique is described whereby input/output (I/O) address translation functions are implemented so as to enable information flow to proceed while systems are set to either extended addressing mode or compatibility mode. Although the I/O address translation process is similar to that used in systems functioning in non-extended mode (compatibility mode), the method involves the fact that extended architecture provides for 256 address spaces of 16 megabytes each. If segment registers were to be used for mapping, as is normally done in compatibility mode, a maximum system would require two-million four-byte registers. Also, using segment registers, an address space is always fixed at the maximum size. By using storage resident segment tables, each address space can vary from two kilobytes to 16 megabytes.

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Input/Output Address Translation for Computer Systems With Extended Memory Addressing

A technique is described whereby input/output (I/O) address translation functions are implemented so as to enable information flow to proceed while systems are set to either extended addressing mode or compatibility mode. Although the I/O address translation process is similar to that used in systems functioning in non-extended mode (compatibility mode), the method involves the fact that extended architecture provides for 256 address spaces of 16 megabytes each. If segment registers were to be used for mapping, as is normally done in compatibility mode, a maximum system would require two-million four-byte registers. Also, using segment registers, an address space is always fixed at the maximum size. By using storage resident segment tables, each address space can vary from two kilobytes to 16 megabytes. To support hardware translation using storage resident segment tables, an address space array is used. (See page 1477.) The address space array has an entry for each address space with each address entry containing a pointer to address the beginning of the segment table and a number specifying the current length of the entries. The figure illustrates how the use of the address space array ties in to the segment tables so that address translation I/O can take place for both extended addressing mode and compatibility mode. Extended processor status word (EPSW) bits 07 and 09 are us...