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Extending the Addressing Capabilities of the IBM Series/1 to 32 Bits

IP.com Disclosure Number: IPCOM000061649D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 6 page(s) / 24K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

A technique is described whereby the total logical addressability of the IBM Series/1 is extended from 20 bits (1 megabyte) to 32 bits (4 gigabytes). The extension divides the total two gigabytes of addressing capability into 256 address spaces, each having an addressing capability of from two kilobytes to 16 megabytes. The technique described herein allows the current 16-bit IBM Series/1 to not only support existing software programs, but to enable new software programs having 24-bit addressability to run concurrently with the current programs. In addition, the concept supports all existing input/output attachments. The extension supports 16 megabytes of real storage, all of which can be addressed using real, non-translated addresses.

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Extending the Addressing Capabilities of the IBM Series/1 to 32 Bits

A technique is described whereby the total logical addressability of the IBM Series/1 is extended from 20 bits (1 megabyte) to 32 bits (4 gigabytes). The extension divides the total two gigabytes of addressing capability into 256 address spaces, each having an addressing capability of from two kilobytes to 16 megabytes. The technique described herein allows the current 16-bit IBM Series/1 to not only support existing software programs, but to enable new software programs having 24-bit addressability to run concurrently with the current programs. In addition, the concept supports all existing input/output attachments. The extension supports 16 megabytes of real storage, all of which can be addressed using real, non-translated addresses. In prior art, only one megabyte of real storage was supported, of which only the low-order 64 kilobytes were addressable using real addresses. Described herein are the various mechanisms and techniques used to implement the extended addressing function. For detailed descriptions of the major operational mechanisms, reference should be made to the articles on pages 1474-1493 of this issue. The following eleven items represent the changes and additions made to the IBM Series/1 architecture to provide for the extended addressing capability: 1. The number of address spaces is increased from 16 (four- bit keys) to 256 (8-bit System Identifier [SID]). 2. Individual address spaces are increased from 64K bytes (16-bit address) to 16M bytes (24-bit address). 3. Real storage addressability, with the Translator disabled, is increased from 64K bytes to 16M bytes. 4. Processor segmentation registers are replaced by segment tables, which reside in real memory. 5. The eleven-word level status block [LSB] (22 bytes) is increased to eleven double words (44 bytes). 6. The processor status word (PSW) is increased to 32 bits. 7. The level status word (register) is increased to 32 bits. 8. Bit 09 in the PSW is designated to indicate the operational mode of the system. When on, it indicates extended mode. When off, it indicates compatibility mode. 9. Bit 21 in the LSR is defined to indicate the mode of execution for the program resident on level. When on, it indicates extended mode. When off, it indicates compatibility mode.
10. An optional address translation cache is provided to enhance performance during storage accesses. 11. Some instructions have been redefined and others have been added to enhance the management of the addresses as a double word data type. A significant feature of the extended addressing capability is the way address space is managed. This involves two types of address spaces: Real and Logical.

Programs executed using Logical addresses are translated dynamically, by the hardware, to Real addresses during run time. When the translator is off, programs are executed using Real addresses with the capability of accessing 16M bytes. Whe...