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Self-Isolating Phase Cutoff Circuit

IP.com Disclosure Number: IPCOM000061674D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

A self-isolating bootstrap driver circuit is described in which the reset phase is locally isolated to reduce power dissipation. Referring to the circuit diagram (Fig. 1), inverter driver 2 is the output section of a standard phase driver. The remainder of the circuit is the self-isolating phase cut-off circuit. Fig. 2 is a phase waveform timing diagram, wherein P2 = Phase fire, P4 = Phase Reset, P6 = Phase Preset, P8 = Phase Reset Prime, and P10 = Phase Off. Transistor T1 is a self-bootstrap device. Transistor T3 precharges the gate of transistor T1 to a voltage Vg equal to the difference between supply voltage (Vdd) and the threshold voltage (Vt) of transistor T3, i.e., Vg = Vdd - Vt. Vdd-gated isolation transistor T2 provides boosted voltage isolation on node n1 from node n2. Transistors T4 and T5 are pull-down devices.

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Self-Isolating Phase Cutoff Circuit

A self-isolating bootstrap driver circuit is described in which the reset phase is locally isolated to reduce power dissipation. Referring to the circuit diagram (Fig.
1), inverter driver 2 is the output section of a standard phase driver. The remainder of the circuit is the self-isolating phase cut-off circuit. Fig. 2 is a phase waveform timing diagram, wherein P2 = Phase fire, P4 = Phase Reset, P6 = Phase Preset, P8 = Phase Reset Prime, and P10 = Phase Off. Transistor T1 is a self-bootstrap device. Transistor T3 precharges the gate of transistor T1 to a voltage Vg equal to the difference between supply voltage (Vdd) and the threshold voltage (Vt) of transistor T3, i.e., Vg = Vdd - Vt. Vdd-gated isolation transistor T2 provides boosted voltage isolation on node n1 from node n2. Transistors T4 and T5 are pull-down devices. As shown in Fig. 2, phase P4 rises and passes a full Vdd level voltage to phase P8 as node n1 self-bootstraps. Phase P6 is then lowered. Phase P10 rises later to reset phase P8. Since node n2 is at voltage V = Vdd - Vt, T5 turns on before T4 as phase P10 approaches Vt. Node n2 then begins to drop, turning transistor T2 on and rapidly pulling node n1 down to match the voltage on node n2. Transistor T1 is thus turned off, isolating phase P8 from phase P4. As phase P10 continues to rise and node n2 drops, transistor T4 turns on, which pulls phase P8 to ground through transistor T5. In this circuit, the fall of p...