Browse Prior Art Database

Memory Card

IP.com Disclosure Number: IPCOM000061679D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Davenport, CS: AUTHOR [+2]

Abstract

A method of obtaining a high density memory card where space and power are essential is described and shown in the figure. This card includes all the buffering, demultiplexing, and decoding that is required and operates from a single power source of +5 V. The design of this card allows the potential of plugging in a maximum of five cards to obtain 640K bytes of data. The card contains a static memory array that is 8 bits wide and 128K address positions deep. The interface consists of 17 address lines and 10 control lines. There are 16 static CMOS RAM modules in a package. All of the supporting and control logics are also on the card. The high density of the card is obtained by using surface-mounted components on both sides of the PC card. The 8 low-order bits are multiplexed with the address to form the data bus.

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Memory Card

A method of obtaining a high density memory card where space and power are essential is described and shown in the figure. This card includes all the buffering, demultiplexing, and decoding that is required and operates from a single power source of +5 V. The design of this card allows the potential of plugging in a maximum of five cards to obtain 640K bytes of data. The card contains a static memory array that is 8 bits wide and 128K address positions deep. The interface consists of 17 address lines and 10 control lines. There are 16 static CMOS RAM modules in a package. All of the supporting and control logics are also on the card. The high density of the card is obtained by using surface-mounted components on both sides of the PC card. The 8 low-order bits are multiplexed with the address to form the data bus. These lines are bidirectional and are shared between address and data. The least significant bits
(8) are demultiplexed from the address/data bus by the ALE signal at the beginning of each cycle. These bits, along with the buffered address bits (A8- A12) go to each memory chip. Address bits A13-A16 and the card select signal are decoded to select the appropriate chip. The MEMW line instructs the addressed memory to store the present data on the data bus in memory. The MEMR line instructs the addressed memory device to place its data on the data bus and control the direction of the data. The card can operate within a minimum time cycle of 800...