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Semiconductor Wafer Process Contamination Gettering

IP.com Disclosure Number: IPCOM000061681D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 18K

Publishing Venue

IBM

Related People

Berry, WS: AUTHOR [+2]

Abstract

This article describes a technique for gettering impurities by controlled generation of misfit dislocations in epitaxial silicon wafers. In general, the gettering of impurities during a LSI or VLSI manufacturing process greatly improves production yields. Techniques such as argon implant, mechanical damage on the back side of a wafer, and controlled precipitation of interstitial oxygen are widely used to create stacking and dislocation faults for gettering sites. By using the method to be described, a high density network of dislocation faults is created at a controlled depth below the active device area. When the doping concentrations of epitaxial silicon and monocrystalline silicon are different, a mechanical stress is created at the layer interface due to a crystalline lattice mismatch between the two layers.

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Semiconductor Wafer Process Contamination Gettering

This article describes a technique for gettering impurities by controlled generation of misfit dislocations in epitaxial silicon wafers. In general, the gettering of impurities during a LSI or VLSI manufacturing process greatly improves production yields. Techniques such as argon implant, mechanical damage on the back side of a wafer, and controlled precipitation of interstitial oxygen are widely used to create stacking and dislocation faults for gettering sites. By using the method to be described, a high density network of dislocation faults is created at a controlled depth below the active device area. When the doping concentrations of epitaxial silicon and monocrystalline silicon are different, a mechanical stress is created at the layer interface due to a crystalline lattice mismatch between the two layers. The number of dislocations formed depends upon the difference in both the lattice constants and thicknesses of the two layers. If this stress is large enough, misfit dislocations may form at the interface at elevated temperatures. Thus, by choosing the right substrate doping concentration and epitaxial silicon thickness, misfit dislocations will be formed. When boron is used as a dopant for both the epitaxial silicon layer and the silicon substrate, the minimum epitaxial silicon thickness needed to create misfit dislocations is expressed as a function of the boron concentration in the substrate. (It is a...