Browse Prior Art Database

Coupled Channel Interference Device

IP.com Disclosure Number: IPCOM000061682D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Hartstein, AM: AUTHOR

Abstract

This article describes a coupled channel, transistor-like device where two parallel electron channels are provided that are quantum mechanically coupled so that electrons can tunnel between them. In such a structure, the electron wave functions will be coherent in all regions except where a gate is positioned. A signal on a gate over one channel will control the wave function in that channel to produce constructive or destructive interference and thereby to control the conductance of the channels. Since the wave functions are coherent in the regions outside of the gate, the effective device size is the size of the gate. A lithographic version of the structure is shown in Fig. 1. (Image Omitted) where the dimension "d" is small enough for quantum mechanical tunneling. The device of Fig. 1 is shown in cross section in Fig. 2.

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Coupled Channel Interference Device

This article describes a coupled channel, transistor-like device where two parallel electron channels are provided that are quantum mechanically coupled so that electrons can tunnel between them. In such a structure, the electron wave functions will be coherent in all regions except where a gate is positioned. A signal on a gate over one channel will control the wave function in that channel to produce constructive or destructive interference and thereby to control the conductance of the channels. Since the wave functions are coherent in the regions outside of the gate, the effective device size is the size of the gate. A lithographic version of the structure is shown in Fig. 1.

(Image Omitted)

where the dimension "d" is small enough for quantum mechanical tunneling. The device of Fig. 1 is shown in cross section in Fig. 2.

(Image Omitted)

A silicon substrate is used with an SiO2 insulator for the gate region. The SiO2 pedestal (P) can be defined by electron beam lithography or by "edge" techniques. The gate electrodes A and B are of conducting material, such as polysilicon or a metal. Regions C and D are insulating layers, most easily formed by oxidizing the electrode regions A and B. Where A and B are heavily doped polysilicon, then C and D would be SiO2 layers. In contacting, after the SiO2 pedestal P has been formed, gate A is deposited by angle deposition on one side of P in Fig. 3. The associated contact electrode Ac is deposited through a liftoff mask, and the mask is removed leaving A and Ac in contact. Electrode A...