Browse Prior Art Database

Method to Reconfigure Logic Signal Paths

IP.com Disclosure Number: IPCOM000061699D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Busch, RE: AUTHOR [+3]

Abstract

A method of reconfiguring logic trees by means of personalization using fuse decoding is disclosed. A specific implementation of the method is address steering in a random-access memory (RAM) where either normal or redundant elements are used without an access penalty. As memory data rates continue to be shortened, any additional delays encountered by redundancy schemes become intolerable. By steering a fuse-programmed address to a redundant circuit column in a RAM, the redundant column is enabled. Also, by permanently disabling a replaced address so that the results of a compare circuit are not in the access path, the delay encountered is confined to the R/C delay of address-steering transistors. Fig. 1 shows a block diagram of the redundancy scheme for a RAM.

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Method to Reconfigure Logic Signal Paths

A method of reconfiguring logic trees by means of personalization using fuse decoding is disclosed. A specific implementation of the method is address steering in a random-access memory (RAM) where either normal or redundant elements are used without an access penalty. As memory data rates continue to be shortened, any additional delays encountered by redundancy schemes become intolerable. By steering a fuse-programmed address to a redundant circuit column in a RAM, the redundant column is enabled. Also, by permanently disabling a replaced address so that the results of a compare circuit are not in the access path, the delay encountered is confined to the R/C delay of address- steering transistors. Fig. 1 shows a block diagram of the redundancy scheme for a RAM. Fuse decode information is stored in a redundancy decoder with latches. The latches are written during initial store (write), after chip power up, and remain unchanged for the duration of the time power is applied. All of the memory addresses must have been scanned before the redundancy fuse compare and encoder circuit outputs are no longer needed. It is possible, once the latches are written, to save power by disabling these circuits.

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_ 7) The memory array has regular and redundant column circuits. 8) Bit switch transistors are used to connect the appropriate data path in memory for a read or write cycle, and only one bit switch is on at a time. Fig. 2 shows the column decoder circuit details. The function of this circuit is to control the bit switch transistors which connect the memory array to the appropriate data path. If the input address turns on transistors T4 through T7, node CD is pulled low. NOR gates NOR1 and NOR2 can pass either sum of redundancy selected (SRS) or sum of redundancy not selected (SRNS) pulses from the encoder. If a redundant address is selected, SRS pulses low and T1 is turned on to set column decoder latch (CDn). If a redundant address is not selected, SRNS pulses low and T2 is turned on to reset column decoder latch CDn . When the column decoder latch is set, it will provide a high input level to NOR3, disabling a bit switch selected by the address lines. A reset column decoder latch allows node CD to control the bit switch selected by the address lines. Fig. 3 shows one of a plurality of redundancy decoder circuits with a latch. The circuit is repeated for each redundant address available, and the latches are used to steer the fuse- programmed...