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Scan Methodology on CMOS Products

IP.com Disclosure Number: IPCOM000061739D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Du Pasquier, M: AUTHOR [+2]

Abstract

In European Patent Application No. 83430043.6 (Publication Number 146661), a methodology has been disclosed to diagnose failures occurring in LSSD (Level Sensitive Scan Design) chains. This method was based on DC variations induced on Idd supply current during the loading of the chain. Nevertheless, this method was not applicable on CMOS products because the global consumption of a CMOS chip is theoretically null. Since then, this method has been successfully adapted to CMOS and diagnostics can be run on this family now. Basically, the NMOS method consisted in measuring the supply current value before and after the switching of each latch of the chain. The rational is that each time a latch switches, some transistors turn on or off inside the latch and in the circuits driven by the latch.

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Scan Methodology on CMOS Products

In European Patent Application No. 83430043.6 (Publication Number 146661), a methodology has been disclosed to diagnose failures occurring in LSSD (Level Sensitive Scan Design) chains. This method was based on DC variations induced on Idd supply current during the loading of the chain. Nevertheless, this method was not applicable on CMOS products because the global consumption of a CMOS chip is theoretically null. Since then, this method has been successfully adapted to CMOS and diagnostics can be run on this family now. Basically, the NMOS method consisted in measuring the supply current value before and after the switching of each latch of the chain. The rational is that each time a latch switches, some transistors turn on or off inside the latch and in the circuits driven by the latch. The induced delta, which could be very small, could be measured with a 100 nA resolution ammeter. The operation was very simple: the chain had to be cleared first, with loading zeros in it. Then the scan input was turned to one, and a first measurement of the supply current was performed. Then a measurement loop was started which consisted in pulsing A clock, measuring Idd, pulsing B clock, and measuring Idd. When the data had stuck on the fault, the displayed difference became null. Since the shift clocks were used to propagate the information, it was easy to know on which latch the data was stopped. But this method cannot be applied to CMOS designs. The solution is the following. Each time you change a logic state in a CMOS chip, the switching of the elementary inverters creates a small transient current flow. If the chip is fed through a 10,000 ohm resistor, the Vdd supply will not be able to maintain the supply voltage instantaneously, and the transient current will be sunk from the capacitance of the Vdd node of the chip. The result will be a negative step on the Vdd, the amplitude of which can be magnified, then digitized with a sample-and-hold circuit connected to a digital voltmeter. The time constant of the spike can be up to a few microseconds, which allows the sample- and-hold circuit to operate in the best condition. In practice, if we call "sublatch" the master and slave parts of the LSSD latch, the switching of each sublatch will happen on the leading edge of each A and B clock. The step induced by the switching of the clock tree wil...