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Exhaustive Test of a Bus Interface

IP.com Disclosure Number: IPCOM000061754D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Orengo, G: AUTHOR [+4]

Abstract

A processor P (Fig. 1) is connected to adapters A1...An, by a bus through a redrive card R. This bus is composed of 3 parts. -Tags out from P to adapters. -Tags in from adapters to P. -Data (2 bytes) which are bidirectional. The data transfer protocol is done via the tag lines. Checkers are implemented in the interface part I of P. They verify data parities and tag sequencing, and generate return codes to P according to the checkings results. For reliability purposes, all the checkers must be verified at the machine Initial Program Loading (IPL). To do that, the processor, which is already master of the tags out and the data (in outbound transfer), must be able to drive also the tags in, which are under adapter control.

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Exhaustive Test of a Bus Interface

A processor P (Fig. 1) is connected to adapters A1...An, by a bus through a redrive card R. This bus is composed of 3 parts. -Tags out from P to adapters. - Tags in from adapters to P. -Data (2 bytes) which are bidirectional. The data transfer protocol is done via the tag lines. Checkers are implemented in the interface part I of P. They verify data parities and tag sequencing, and generate return codes to P according to the checkings results. For reliability purposes, all the checkers must be verified at the machine Initial Program Loading (IPL). To do that, the processor, which is already master of the tags out and the data (in outbound transfer), must be able to drive also the tags in, which are under adapter control. It also must read the tags out that it sends to the adapters to know exactly the bus status and decide to validate or not the parity check. This implies that all the bus lines become bidirectional as seen by the processor. To do this, drivers-receivers are implemented on all the tag (in and out) lines and a wrap function is done by means of a latch L1 (Fig. 2) which is set by a processor- initiated operation PIO. This wrap line enables all the drivers of I. A tag-in register is implemented in I, and it is used to simulate the adapters' behavior in wrap mode. It is also written by an operation PIO and has no use in the machine functional mode. On the other side, the checking must be done with a bus free of the di...