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Browse Prior Art Database

Array Power Down Scheme

IP.com Disclosure Number: IPCOM000061760D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR

Abstract

This article describes a means for powering-down the stand-by current of a bipolar memory cell to enable low current stress testing. Bipolar memory cells such as Complementary-Transistor Switch or Harper-PNP types are sensitive to leakages and device degradation due to their low current attribute. To improve the reliability of the chip, in arrays using such cells, it is desirable to have a circuit means on-chip to power down the memory cells for stress testing. Power-down circuitry enables the array's stand-by current to be switched from its normal value to a lower, predetermined magnitude (e.g., an order of magnitude lower). Operating at a reduced current level, the memory cells are stressed for low current leakage sensitivity.

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Array Power Down Scheme

This article describes a means for powering-down the stand-by current of a bipolar memory cell to enable low current stress testing. Bipolar memory cells such as Complementary-Transistor Switch or Harper-PNP types are sensitive to leakages and device degradation due to their low current attribute. To improve the reliability of the chip, in arrays using such cells, it is desirable to have a circuit means on-chip to power down the memory cells for stress testing. Power-down circuitry enables the array's stand-by current to be switched from its normal value to a lower, predetermined magnitude (e.g., an order of magnitude lower). Operating at a reduced current level, the memory cells are stressed for low current leakage sensitivity. This procedure will also simulate the effects of reduction in cell current caused by device degradation or 'current-hogging' problems. Fig. 1 shows the circuitry of the disclosed array power-down scheme. The array, for purposes of illustration, is assumed to be organized in 128 word lines by 128 cells. Each word line has a resistor RH connected to its upper line WL and a resistor RL to its drain line DL. RH and RL form a voltage divider to define word line stand-by voltage levels. They are also used to supply current to the cells on the word line. Unlike existing designs in which the resistors RL are connected to the VEE power supply, thereby setting word line stand-by current to a fixed magnitude, the resistors RL are connected instead to a switchable power bus, PB, thereby enabling different current levels to be applied to the cells. Switching of the PB bus is controlled by the power-down receiver shown in Fig. 2, in conjunction with two (or more, depending on power distribution needs) open-collector transistor pull-downs. Current applied to the word lines during power-down test is set by the resistors RN. To test switching of the power-down receiver, as well as to monitor the PB bus voltage level, a sense output is connected directly to the PB line. Additional RN resistors (as indicated by the dotted line) are also provided in order to further extend the range of current levels that are applied to the word lines. These RN resistors can be selected through chip personalization change. The two modes of operation can be described as follows: 1) Normal Mode: The input is either tied up or left floating. The output PD of the power-down receiver is high, hence turn...