Browse Prior Art Database

Self-Checking ECC Module for a Processor Memory

IP.com Disclosure Number: IPCOM000061761D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Dauby, A: AUTHOR [+3]

Abstract

The purpose of the memory checking described in this article is to verify that the encoded pattern presented to the memory, by the error correcting code (ECC) module, during a write, has the appropriate configuration. The checking is done on the word placed on the data bus and thus the drivers and the receivers of the nets are also checked.. The error correcting circuit (Fig. 1) has been split into two independent parts. One is devoted to the encoding of the words to be stored, while the other one is the correcting path that generates the syndrome and performs the correction whenever it is necessary before the data is delivered to the processor. The word placed on the data bus during a write is the data coming from the processor along with the ECC bits that were just computed by the encoding path.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 91% of the total text.

Page 1 of 2

Self-Checking ECC Module for a Processor Memory

The purpose of the memory checking described in this article is to verify that the encoded pattern presented to the memory, by the error correcting code (ECC) module, during a write, has the appropriate configuration. The checking is done on the word placed on the data bus and thus the drivers and the receivers of the nets are also checked.. The error correcting circuit (Fig. 1) has been split into two independent parts. One is devoted to the encoding of the words to be stored, while the other one is the correcting path that generates the syndrome and performs the correction whenever it is necessary before the data is delivered to the processor. The word placed on the data bus during a write is the data coming from the processor along with the ECC bits that were just computed by the encoding path. This word is going to be stored at the memory location given by the address bus. When, later on, it is fetched, one or two bits may differ from what was written. The ECC read path will take care of that and finally restore the wrong bits to their original value. During a write, because of the ECC structure, the opportunity is given to have an auto-check of the ECC hardware and environment by resampling the data bus with the read part of the module. If the word is properly encoded and nothing prevents it from getting the good levels on the data bus, an all-zero syndrome should be detected by the read part of the ECC. Whenev...